74HC4020DB [NXP]
14-stage binary ripple counter; 14级二进制纹波计数器
| 型号： | 74HC4020DB |
| 厂家： | 
NXP |
| 描述： | 14-stage binary ripple counter |
| 文件： | 总7页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4020
14-stage binary ripple counter
September 1993
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
14-stage binary ripple counter
74HC/HCT4020
The 74HC/HCT4020 are 14-stage binary ripple counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and twelve fully buffered parallel
outputs (Q0, Q3 to Q13).
FEATURES
• Output capability: standard
• ICC category: MSI
The counter is advanced on the HIGH-to-LOW transition of
CP.
GENERAL DESCRIPTION
The 74HC/HCT4020 are high-speed Si-gate CMOS
devices and are pin compatible with the “4020” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CL = 15 pF; VCC = 5 V
CP to Q0
11
6
15
ns
Qn to Qn+1
6
ns
MR to Qn
17
19
52
3.5
20
ns
fmax
CI
maximum clock frequency
input capacitance
101
3.5
19
MHz
pF
CPD
power dissipation capacitance per package
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2
Philips Semiconductors
Product specification
14-stage binary ripple counter
74HC/HCT4020
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 Q0, Q3 to Q13
parallel outputs
ground (0 V)
8
GND
CP
10
11
16
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
positive supply voltage
MR
VCC
page
RCTR14
9
7
0
3
5
CT=0
4
6
13
12
14
15
1
CT
2
3
13
MGA829
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
14-stage binary ripple counter
74HC/HCT4020
FUNCTION TABLE
INPUTS
MR
OUTPUTS
CP
Q0, Q3 to Q13
↑
↓
X
L
L
H
no change
count
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Fig.4 Functional diagram.
↑ = LOW-to-HIGH clock
transition
↓ = HIGH-to-LOW clock
transition
Fig.5 Logic diagram.
Fig.6 Timing diagram.
September 1993
4
Philips Semiconductors
Product specification
14-stage binary ripple counter
74HC/HCT4020
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q0
39
14
11
140
28
24
175
35
30
210
42
36
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.7
4.5
6.0
t
PHL/ tPLH propagation delay
Qn to Qn+1
22
8
6
75
15
13
95
19
16
110
22
19
2.0 Fig.7
4.5
6.0
tPHL
propagation delay
MR to Qn
55
20
16
170
34
29
215
43
37
225
51
43
2.0 Fig.8
4.5
6.0
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.7
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
11
4
3
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
tW
master reset pulse width 80
17
6
5
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
HIGH
16
14
trem
removal time
MR to CP
50
10
9
6
2
2
65
13
11
75
15
13
2.0 Fig.8
4.5
6.0
fmax
maximum clock pulse
frequency
6.0
30
35
30
92
109
4.8
24
28
4.0
20
24
MHz 2.0 Fig.7
4.5
6.0
September 1993
5
Philips Semiconductors
Product specification
14-stage binary ripple counter
74HC/HCT4020
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
CP
MR
0.85
1.10
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q0
18
8
36
15
45
15
45
19
56
19
54
22
68
22
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.7
4.5 Fig.8
4.5 Fig.7
4.5 Fig.7
4.5 Fig.8
4.5 Fig.8
t
PHL/ tPLH propagation delay
Qn to Qn+1
tPHL
propagation delay
MR to Qn
22
7
t
THL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
20
7
25
25
13
20
30
30
15
17
tW
master reset pulse width 20
HIGH
8
trem
fmax
removal time
MR to CP
10
2
maximum clock pulse
frequency
25
47
MHz 4.5 Fig.7
September 1993
6
Philips Semiconductors
Product specification
14-stage binary ripple counter
74HC/HCT4020
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays
and the master reset to clock (CP) removal time.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
7
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