74HC4024D,652_技术文档

74HC4024

7-stage binary ripple counter

Rev. 6 — 23 August 2012

Product data sheet

1. General description

The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024

of the 4000B series. The 74HC4024 is specified in compliance with JEDEC

standard no. 7A.

The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to

Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears

all counter stages and forces all outputs LOW, independent of the state of CP. Each

counter stage is a static toggle flip-flop.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock

rise and fall times.

2. Features and benefits

 Low-power dissipation

 Complies with JEDEC standard no. 7A

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V.

 Multiple package options

 Specified from 40 C to +80 C and from 40 C to +125 C.

3. Applications

 Frequency dividing circuits

 Time delay circuits.

74HC4024

NXP Semiconductors

7-stage binary ripple counter

4. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range

40 C to +125 C

Name

DIP14

SO14

Description

Version

74HC4024N

74HC4024D

plastic dual in-line package; 14 leads (300 mil) SOT27-1

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

SOT337-1

SOT402-1

74HC4024DB

74HC4024PW

40 C to +125 C

SSOP14

plastic shrink small outline package; 14 leads;

body width 5.3 mm

TSSOP14

plastic thin shrink small outline package;

14 leads; body width 4.4 mm

5. Functional diagram

Q6

Q5

Q4

Q3

Q2

3

4

5

6

9

7-STAGE

COUNTER

CTR7

CT

12

11

9

Q0

0

1

2

11

9

1

2

Q1

Q2

Q3

Q4

Q5

Q6

CP

+

Q1 11

Q0 12

6

5

MR

CT = 0

4

CP

1

MR

3

6

001aab907

2

001aab906

001aab908

Fig 1. Logic symbol

Fig 2. Functional diagram

Fig 3. IEC logic symbol

Q

FF

1

Q

FF

2

FF

3

FF

4

FF

5

FF

6

FF

7

CP

T

Q

RD

MR

Q0

Q1

Q2

Q3

Q4

Q5

Q6

001aab909

Fig 4. Logic diagram

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

2 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

6. Pinning information

6.1 Pinning

74HC4024

1

2

3

4

5

6

7

14

13

12

11

10

9

CP

MR

Q6

V

CC

n.c.

Q0

Q5

Q1

Q4

n.c.

Q2

Q3

8

GND

n.c.

001aab905

Fig 5. Pin configuration

6.2 Pin description

Table 2.

Pin description

Symbol

1

Description

CP

clock input (HIGH-to-LOW, edge-triggered)

master reset input (active HIGH)

parallel output

MR

2

Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0

3, 4, 5, 6, 9, 11, 12

GND

n.c.

7

ground (0 V)

8, 10, 13

14

not connected

V_CC

positive supply voltage

7. Functional description

Table 3.

Input

MR

Function table^[1]

Output

Qn

CP

X

H

L



no change

count



[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

 = LOW-to-HIGH clock transition;

= HIGH-to-LOW clock transition.

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

3 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7

Unit

V

supply voltage

0.5

input clamping current

output clamping current

output current

V_I< 0.5 V or V_I> V_CC+ 0.5 V

V_O< 0.5 V or V_O> V_CC+ 0.5 V

V_O= 0.5 V to V_CC+ 0.5 V

-

20

25

50

mA

C

I_OK

-

I_O

-

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

50

-

storage temperature

total power dissipation

65

+150

750

500

[1]

[2]

[3]

DIP14 package

-

mW

SO14 package

SSOP14 and TSSOP14 package

[1] For DIP16 package: P_totderates linearly with 12 mW/K above 70 C.

[2] For SO16 package: P_totderates linearly with 8 mW/K above 70 C.

[3] For (T)SSOP16 packages: P_totderates linearly with 5.5 mW/K above 60 C.

9. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

input voltage

output voltage

2.0

5.0

6.0

V

V_I

0

-

V_CC

625

139

83

V

V_O

0

-

V

t/V

input transition rise and fall

rate

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

ns/V

C

-

1.67

-

T_amb

ambient temperature

40

+125

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

4 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

10. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

T_amb= 25 C

V_IH

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level input voltage

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

1.5

1.2

2.4

3.2

0.8

2.1

2.8

-

V

3.15

-

4.2

-

V_IL

LOW-level input voltage

-

0.5

1.35

1.8

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= 20 A; V_CC= 2.0 V

1.9

2.0

-

V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

I_O= 4 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

4.4

4.5

5.9

6.0

3.98

5.48

4.32

5.81

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

-

0

0.1

0.26

0.1

8.0

-

V

0

V

I_O= 20 A; V_CC= 6.0 V

0

V

I_O= 4 mA; V_CC= 4.5 V

0.15

0.16

-

V

I_O= 5.2 mA; V_CC= 6.0 V

V_I= V_CCor GND; V_CC= 6.0 V

V_I= V_CCor GND; I_O= 0 A; V_CC= 6.0 V

V

I_I

input leakage current

supply current

A

pF

I_CC

C_I

-

input capacitance

3.5

T_amb= 40 C to +85 C

V_IHHIGH-level input voltage

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

1.5

-

V

3.15

-

4.2

-

V_IL

LOW-level input voltage

-

0.5

1.35

1.8

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= 20 A; V_CC= 2.0 V

1.9

-

V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

I_O= 4 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

4.4

5.9

3.84

5.34

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

5 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

Table 6.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

LOW-level output voltage V_I= V_IHor V_IL

I_O= 20 A; V_CC= 2.0 V

Conditions

Min

Typ

Max

Unit

V_OL

-

0.1

V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

0.1

V

0.1

V

I_O= 4 mA; V_CC= 4.5 V

0.33

1.0

80

V

I_O= 5.2 mA; V_CC= 6.0 V

V

I_I

input leakage current

supply current

V_I= V_CCor GND; V_CC= 6.0 V

V_I= V_CCor GND; I_O= 0 A; V_CC= 6.0 V

A

I_CC

T_amb= 40 C to +125 C

V_IHHIGH-level input voltage

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

1.5

-

V

3.15

-

4.2

-

V_IL

LOW-level input voltage

-

0.5

1.35

1.8

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= 20 A; V_CC= 2.0 V

1.9

4.4

5.9

3.7

5.2

-

V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

I_O= 4 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

-

0.1

0.4

1.0

160

V

I_O= 20 A; V_CC= 6.0 V

V

I_O= 4 mA; V_CC= 4.5 V

V

I_O= 5.2 mA; V_CC= 6.0 V

V_I= V_CCor GND; V_CC= 6.0 V

V_I= V_CCor GND; I_O= 0 A; V_CC= 6.0 V

V

I_I

input leakage current

supply current

A

I_CC

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

6 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

11. Dynamic characteristics

Table 7.

Dynamic characteristics

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF; see Figure 7.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= 25 C

[1]

t_pd

propagation delay

CP to Q0; see Figure 6

V_CC= 2.0 V

-

47

17

14

175

35

30

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 5.0 V; C_L= 15 pF

Qn to Qn+1; see Figure 6

V_CC= 2.0 V

[1]

-

25

9

80

16

14

ns

V_CC= 4.5 V

V_CC= 6.0 V

7

t_PHL

HIGH to LOW

propagation delay

MR to Q0; see Figure 6

V_CC= 2.0 V

-

63

23

18

200

40

ns

V_CC= 4.5 V

V_CC= 6.0 V

34

[2]

t_t

transition time

pulse width

see Figure 6

V_CC= 2.0 V

-

19

7

75

15

13

ns

V

_CC= 4.5 V

V_CC= 6.0 V

CP HIGH or LOW; see Figure 6

V_CC= 2.0 V

6

t_W

80

16

14

17

6

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

5

MR HIGH; see Figure 6

V_CC= 2.0 V

80

16

14

22

8

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

6

t_rec

recovery time

MR to CP; see Figure 6

V_CC= 2.0 V

50

10

9

6

2

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

f_max

maximum frequency

CP; see Figure 6

V_CC= 2.0 V

6.0

30

35

-

27

82

98

90

25

-

MHz

pF

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 5.0 V; C_L= 15 pF

V_I= GND to V_CC

[3]

C_PD

power dissipation

capacitance

-

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

7 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

Table 7.

Dynamic characteristics …continued

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF; see Figure 7.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= 40 C to +85 C

[1]

t_pd

propagation delay

CP to Q0; see Figure 6

V_CC= 2.0 V

-

220

44

ns

V_CC= 4.5 V

V_CC= 6.0 V

37

Qn to Qn+1; see Figure 6

V_CC= 2.0 V

-

100

20

ns

V_CC= 4.5 V

V_CC= 6.0 V

17

t_PHL

HIGH to LOW

propagation delay

MR to Q0; see Figure 6

V_CC= 2.0 V

-

250

50

ns

V_CC= 4.5 V

V_CC= 6.0 V

43

[2]

t_t

transition time

pulse width

see Figure 6

V_CC= 2.0 V

-

95

19

16

ns

V_CC= 4.5 V

V_CC= 6.0 V

t_W

CP HIGH or LOW; see Figure 6

V_CC= 2.0 V

100

20

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

17

MR HIGH; see Figure 6

V_CC= 2.0 V

100

20

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

17

t_rec

recovery time

MR to CP; see Figure 6

V_CC= 2.0 V

65

13

11

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

f_max

maximum frequency

CP; see Figure 6

V_CC= 2.0 V

4.8

24

28

-

MHz

V_CC= 4.5 V

V_CC= 6.0 V

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

8 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

Table 7.

Dynamic characteristics …continued

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF; see Figure 7.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= 40 C to +125 C

[1]

t_pd

propagation delay

CP to Q0; see Figure 6

V_CC= 2.0 V

-

265

53

ns

V_CC= 4.5 V

V_CC= 6.0 V

45

Qn to Qn+1; see Figure 6

V_CC= 2.0 V

-

120

24

ns

V_CC= 4.5 V

V_CC= 6.0 V

20

t_PHL

HIGH to LOW

propagation delay

MR to Q0; see Figure 6

V_CC= 2.0 V

-

300

60

ns

V_CC= 4.5 V

V_CC= 6.0 V

51

[2]

t_t

transition time

pulse width

see Figure 6

V_CC= 2.0 V

-

110

22

ns

V_CC= 4.5 V

V_CC= 6.0 V

19

t_W

CP HIGH or LOW; see Figure 6

V_CC= 2.0 V

120

24

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

20

MR HIGH; see Figure 6

V_CC= 2.0 V

120

24

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

20

t_rec

recovery time

MR to CP; see Figure 6

V_CC= 2.0 V

75

15

13

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

9 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

Table 7.

Dynamic characteristics …continued

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF; see Figure 7.

Symbol

Parameter

Conditions

CP; see Figure 6

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

Min

Typ

Max

Unit

f_max

maximum frequency

4.0

20

24

-

MHz

[1] t_pdis the same as t_PLHand t_PHL

[2] t_tis the same as t_THLand t_TLH

.

[3] C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

(C_L V_CC² f_o) = sum of outputs.

12. Waveforms

MR input

CP input

V

M

t

1/f

W

max

t

rec

V

M

t

W

t

PHL

PLH

90 %

Q0 or Qn

output

V

M

10 %

t

TLH

THL

001aab910

Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to

clock (CP) recovery time.

V

_M= 0.5  V_I.

Fig 6. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output

transition times and the maximum clock frequency

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

10 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

V

CC

V

O

I

PULSE

GENERATOR

DUT

C

L

R

T

mna101

Test data is given in Table 8.

Definitions for test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

Fig 7. Test circuit for measuring switching times

Table 8.

Supply

V_CC

Test data

Input

V_I

Load

C_L

t_r, t_f

6 ns

2.0 V

V_CC

50 pF

15 pF

4.5 V

6.0 V

5.0 V

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

11 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

13. Package outline

DIP14: plastic dual in-line package; 14 leads (300 mil)

SOT27-1

D

M

E

A

2

A

1

L

c

e

w M

Z

b

1

(e )

1

b

M

H

14

8

pin 1 index

E

1

7

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

2

(1)

Z

1

UNIT

mm

b

c

D

E

e

L

M

H

w

1

E

max.

min.

max.

1.73

1.13

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

2.2

0.068

0.044

0.021

0.015

0.014

0.009

0.77

0.73

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.087

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT27-1

050G04

MO-001

SC-501-14

Fig 8. Package outline SOT27-1 (DIP14)

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

12 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

14

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

7

e

detail X

w

M

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.75

1.27

0.05

1.05

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Fig 9. Package outline SOT108-1 (SO14)

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

13 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm

SOT337-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

14

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

7

1

detail X

w M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

3

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

1.4

0.9

mm

2

0.25

0.65

1.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT337-1

MO-150

Fig 10. Package outline SOT337-1 (SSOP14)

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

14 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

14

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

7

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig 11. Package outline SOT402-1 (TSSOP14)

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

15 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

14. Abbreviations

Table 9.

Acronym

CMOS

DUT

Abbreviations

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

15. Revision history

Table 10. Revision history

Document ID

74HC4024 v.6

Modifications:

74HC4024 v.5

Modifications:

74HC4024 v.4

74HC4024 v.3

Release date Data sheet status

20120823 Product data sheet

Change notice

Supersedes

-

74HC4024 v.5

• Measurement points added to Figure 8 (errata).

20111209

Product data sheet

-

74HC4024 v.4

• Legal pages updated.

20100929

20041112

Product data sheet

-

74HC4024 v.3

74HC_HCT4024_CNV v.2

74HC_HCT4024 v.1

-

Product data sheet

Product specification

74HC_HCT4024_CNV v.2 19970901

74HC_HCT4024 v.1

19901201

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

16 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

16.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

17 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74HC4024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 23 August 2012

18 of 19

74HC4024

NXP Semiconductors

7-stage binary ripple counter

18. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

Functional description . . . . . . . . . . . . . . . . . . . 3

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

8

9

10

11

12

13

14

15

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 23 August 2012

Document identifier: 74HC4024


型号：	74HC4024D,652
厂家：	NXP
描述：	74HC4024 - 7-stage binary ripple counter SOIC 14-Pin 光电二极管逻辑集成电路触发器
文件：	总19页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HC4024D,652 [NXP]

相关型号：

74HC4024D,653

74HC4024D-Q100

74HC4024D-T

74HC4024D/T3

74HC4024DB

74HC4024DB,112

74HC4024DB,118

74HC4024DB-T

74HC4024N

74HC4024NB

74HC4024PW

74HC4024PW,112