74HC4067N [NXP]
16-channel analog multiplexer/demultiplexer; 16通道模拟多路复用器/多路分解器
| 型号： | 74HC4067N |
| 厂家： | 
NXP |
| 描述： | 16-channel analog multiplexer/demultiplexer |
| 文件： | 总29页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Rev. 03 — 15 October 2007
Product data sheet
1. General description
The 74HC4067; 74HCT4067 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4067B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4067; 74HCT4067 is a 16-channel analog multiplexer/demultiplexer with four
address inputs (S0 to S3), an active-LOW enable input (E), sixteen independent
inputs/outputs (Y0 to Y15) and a common input/output (Z).
The 74HC4067; 74HCT4067 contains sixteen bidirectional analog switches, each with
one side connected to an independent input/output (Y0 to Y15) and the other side
connected to a common input/output (Z).
With pin E = LOW, one of the sixteen switches is selected by pins S0 to S3 (low
impedance ON-state). All unselected switches are in the high-impedance OFF-state.
With pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins
S0 to S3.
The analog inputs/outputs (Y0 to Y15, and Z) can swing between VCC as a positive limit
and GND as a negative limit. VCC to GND may not exceed 10 V.
2. Features
I Low ON resistance:
N 80 Ω (typical) at VCC = 4.5 V
N 70 Ω (typical) at VCC = 6.0 V
N 60 Ω (typical) at VCC = 9.0 V
I Typical ‘break before make’ built-in
3. Applications
I Analog multiplexing and demultiplexing
I Digital multiplexing and demultiplexing
I Signal gating
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC4067
74HC4067N
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
DIP24
plastic dual in-line package; 24 leads (600 mil);
reverse bending
SOT101-1
SOT137-1
SOT340-1
SOT355-1
74HC4067D
SO24
plastic small outline package; 24 leads;
body width 7.5 mm
74HC4067DB
74HC4067PW
74HC4067BQ
SSOP24
TSSOP24
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5 × 5.5 × 0.85 mm
74HCT4067
74HCT4067N
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
DIP24
plastic dual in-line package; 24 leads (600 mil);
reverse bending
SOT101-1
SOT137-1
SOT340-1
SOT355-1
74HCT4067D
SO24
plastic small outline package; 24 leads;
body width 7.5 mm
74HCT4067DB
SSOP24
TSSOP24
plastic shrink small outline package; 24 leads;
body width 5.3 mm
74HCT4067PW −40 °C to +125 °C
74HCT4067BQ −40 °C to +125 °C
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5 × 5.5 × 0.85 mm
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
2 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
5. Functional diagram
10
0
11
0
14
13
16 ×
15
3
Y0
9
15
G16
S0
Y1
10
11
14
13
8
7
S1
S2
S3
Y2
MUX/DMUX
9
0
Y3
6
8
1
2
Y4
5
7
Y5
6
4
3
1
Y6
5
3
4
Y7
4
2
5
3
Y8
6
23
22
21
20
19
18
17
16
2
Y9
7
23
22
21
20
19
18
17
16
Y10
Y11
Y12
Y13
Y14
Y15
8
9
10
11
12
13
14
E
15
1
15
Z
001aag725
001aag726
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Yn
V
CC
V
CC
Z
GND
from
logic
001aag729
Fig 3. Schematic diagram (one switch)
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
3 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
9
8
7
6
5
4
3
2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
S0 10
S1 11
S2 14
S3 13
23 Y8
1-OF-16
DECODER
22 Y9
21 Y10
20 Y11
19 Y12
18 Y13
17 Y14
16 Y15
E
15
1
Z
001aag727
Fig 4. Functional diagram
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
4 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
Y0
Y1
Y2
Y3
Y4
S0
S1
S2
S3
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
E
Z
001aag728
Fig 5. Logic diagram
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
5 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
74HC4067
74HCT4067
74HC4067
terminal 1
index area
74HCT4067
1
2
24
23
22
21
20
19
18
17
16
15
14
13
Z
Y7
V
CC
2
3
23
22
21
20
19
18
17
16
15
14
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
S0
S1
Y8
Y8
Y9
3
Y6
Y9
4
Y10
Y11
Y12
Y13
Y14
Y15
E
4
Y5
Y10
Y11
Y12
Y13
Y14
Y15
E
5
5
Y4
6
6
Y3
7
7
Y2
8
8
Y1
9
9
Y0
(1)
CC
10
11
V
10
11
12
S0
S2
S1
S2
GND
S3
001aag731
001aag730
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 6. Pin configuration for DIP24, SO24, SSOP24 and
TSSOP24
Fig 7. Pin configuration for DHVQFN24
6.2 Pin description
Table 2.
Symbol
Z
Pin description
Pin
1
Description
common input/output
independent input/output 7
independent input/output 6
independent input/output 5
independent input/output 4
independent input/output 3
independent input/output 2
independent input/output 1
independent input/output 0
address input 0
Y7
2
Y6
3
Y5
4
Y4
5
Y3
6
Y2
7
Y1
8
Y0
9
S0
10
11
12
13
14
S1
address input 1
GND
S3
ground (0 V)
address input 3
S2
address input 2
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
6 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
Table 2.
Symbol
E
Pin description …continued
Pin
15
16
17
18
19
20
21
22
23
24
Description
enable input (active LOW)
independent input/output 15
independent input/output 14
independent input/output 13
independent input/output 12
independent input/output 11
independent input/output 10
independent input/output 9
independent input/output 8
supply voltage
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
VCC
7. Functional description
Table 3.
Function table[1]
Inputs
Channel ON
E
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
S3
L
S2
L
S1
L
S0
L
Y0 to Z
Y1 to Z
Y2 to Z
Y3 to Z
Y4 to Z
Y5 to Z
Y6 to Z
Y7 to Z
Y8 to Z
Y9 to Z
Y10 to Z
Y11 to Z
Y12 to Z
Y13 to Z
Y14 to Z
Y15 to Z
-
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
X
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
X
L
H
L
H
H
X
H
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
7 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+11.0
±20
±20
±25
50
Unit
V
[1]
VCC
IIK
supply voltage
−0.5
input clamping current
switch clamping current
switch current
VI < −0.5 V or VI > VCC + 0.5 V
VSW < −0.5 V or VSW > VCC + 0.5 V
VSW = −0.5 V to (VCC + 0.5 V)
-
mA
mA
mA
mA
mA
°C
ISK
-
ISW
ICC
IGND
Tstg
Ptot
-
supply current
-
ground current
-
−50
+150
storage temperature
total power dissipation
−65
Tamb = −40 °C to +125 °C
DIP24 package
[2]
[3]
[4]
[4]
[5]
-
-
-
-
-
-
750
500
500
500
500
100
mW
mW
mW
mW
mW
mW
SO24 package
SSOP24 package
TSSOP24 package
DHVQFN24 package
per switch
P
power dissipation
[1] To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn. In this case there is
no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or GND.
[2] For DIP24 package: Ptot derates linearly with 12 mW/K above 70 °C.
[3] For SO24 package: Ptot derates linearly with 8 mW/K above 70 °C.
[4] For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
[5] For DHVQFN24 package: Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
74HC4067
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
input voltage
switch voltage
rise time
2.0
5.0
10.0
VCC
VCC
1000
500
V
GND
-
V
VSW
tr
GND
-
V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 10.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 10.0 V
-
-
ns
ns
ns
ns
ns
ns
ns
ns
°C
-
6.0
-
-
400
-
-
250
tf
fall time
-
-
1000
500
-
6.0
-
-
400
-
-
250
Tamb
ambient temperature
−40
+25
+125
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
8 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
Table 5.
Recommended operating conditions …continued
Symbol Parameter
74HCT4067
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
input voltage
switch voltage
rise time
4.5
GND
GND
-
5.0
-
5.5
V
VCC
VCC
500
500
+125
V
VSW
tr
-
V
VCC = 4.5 V
VCC = 4.5 V
6.0
6.0
+25
ns
ns
°C
tf
fall time
-
Tamb
ambient temperature
−40
10. Static characteristics
Table 6.
RON resistance per switch for types 74HC4067 and 74HCT4067
VI = VIH or VIL; for test circuit see Figure 8.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
For 74HC4067: VCC − GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
For 74HCT4067: VCC − GND = 4.5 V.
Symbol
Parameter
Conditions
25 °C
Max
−40 °C to +125 °C Unit
Max Max
(85 °C) (125 °C)
Typ
RON(peak)
ON resistance (peak)
Vis = VCC to GND
[1]
[1]
[1]
VCC = 2.0 V; ISW = 100 µA
VCC = 4.5 V; ISW = 1000 µA
VCC = 6.0 V; ISW = 1000 µA
VCC = 9.0 V; ISW = 1000 µA
Vis = GND or VCC
-
-
-
-
Ω
Ω
Ω
Ω
110
95
75
180
160
130
225
200
165
270
240
195
RON(rail)
ON resistance (rail)
VCC = 2.0 V; ISW = 100 µA
VCC = 4.5 V; ISW = 1000 µA
VCC = 6.0 V; ISW = 1000 µA
VCC = 9.0 V; ISW = 1000 µA
150
90
-
-
-
160
140
120
200
175
150
240
210
180
Ω
Ω
Ω
80
70
∆RON
ON resistance mismatch Vis = VCC to GND
between channels
VCC = 2.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
9
8
6
[1] At supply voltages (VCC − GND) approaching 2 V, the analog switch ON resistance becomes extremely non-linear. Therefore it is
recommended that these devices be used to transmit digital signals only, when using these supply voltages.
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
9 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
mnb047
110
(1)
R
ON
(Ω)
V
SW
90
V
CC
70
50
30
10
(2)
(3)
E
V
IL
Yn
Z
GND
V
I
SW
is
001aag733
0
1.8
3.6
5.4
7.2
9.0
V
(V)
is
Vis = 0 V to (VCC − GND)
Vis = 0 V to (VCC − GND)
(1) VCC = 4.5 V
VSW
RON
=
----------
(2) VCC = 6.0 V
(3) VCC = 9.0 V
ISW
Fig 8. Test circuit for measuring RON
Table 7. Static characteristics 74HC4067
Fig 9. Typical RON as a function of input voltage Vis
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-level input voltage
LOW-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
VI = VCC or GND
VCC = 6.0 V
VCC = 10.0 V
1.5
1.2
2.4
3.2
4.7
0.8
2.1
2.8
4.3
-
V
V
V
V
V
V
V
V
3.15
-
4.2
-
6.3
-
VIL
-
-
-
-
0.5
1.35
1.80
2.70
II
input leakage current
-
-
-
-
±0.1
±0.2
µA
µA
IS(OFF)
OFF-state leakage current
VCC = 10.0 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 10
per channel
all channels
-
-
-
-
-
-
±0.1
±0.8
±0.8
µA
µA
µA
IS(ON)
ON-state leakage current
VCC = 10.0 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 11
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
10 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
Table 7.
Static characteristics 74HC4067 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol
ICC
Parameter
Conditions
Min
Typ
Max
Unit
supply current
VI = VCC or GND; Vis = GND or VCC;
Vos = VCC or GND
VCC = 6.0 V
-
-
-
-
8.0
16.0
-
µA
µA
pF
VCC = 10.0 V
-
CI
input capacitance
3.5
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
VI = VCC or GND
VCC = 6.0 V
VCC = 10.0 V
1.5
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
3.15
-
4.2
-
6.3
-
VIL
LOW-level input voltage
-
-
-
-
0.50
1.35
1.80
2.70
II
input leakage current
-
-
-
-
±1.0
±2.0
µA
µA
IS(OFF)
OFF-state leakage current
VCC = 10.0 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 10
per channel
all channels
-
-
-
-
-
-
±1.0
±8.0
±8.0
µA
µA
µA
IS(ON)
ICC
ON-state leakage current
supply current
VCC = 10.0 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 11
VI = VCC or GND; Vis = GND or VCC
;
Vos = VCC or GND
VCC = 6.0 V
-
-
-
-
80.0
160
µA
µA
VCC = 10.0 V
Tamb = −40 °C to +125 °C
VIH
VIL
II
HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
VI = VCC or GND
VCC = 6.0 V
VCC = 10.0 V
1.5
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
3.15
-
4.2
-
6.3
-
LOW-level input voltage
input leakage current
-
-
-
-
0.50
1.35
1.80
2.70
-
-
-
-
±1.0
±2.0
µA
µA
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
11 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
Table 7.
Static characteristics 74HC4067 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IS(OFF)
OFF-state leakage current
VCC = 10.0 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 10
per channel
all channels
-
-
-
-
-
-
±1.0
±8.0
±8.0
µA
µA
µA
IS(ON)
ICC
ON-state leakage current
supply current
VCC = 10.0 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 11
VI = VCC or GND; Vis = GND or VCC
;
Vos = VCC or GND
VCC = 6.0 V
-
-
-
-
160
320
µA
µA
VCC = 10.0 V
Table 8.
Static characteristics 74HCT4067
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
input leakage current
VCC = 4.5 V to 5.5 V
2.0
1.6
1.2
-
-
V
VCC = 4.5 V to 5.5 V
-
-
0.8
±0.1
V
II
VI = VCC or GND; VCC = 5.5 V
µA
IS(OFF)
OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 10
per channel
all channels
-
-
-
-
-
-
±0.1
±0.8
±0.8
µA
µA
µA
IS(ON)
ICC
ON-state leakage current
supply current
VCC = 5.5 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 11
VI = VCC or GND; Vis = GND or VCC
;
-
-
8.0
µA
Vos = VCC or GND; VCC = 4.5 V to 5.5 V
∆ICC
additional supply current
per input pin; VI = VCC − 2.1 V; other inputs
at VCC or GND; VCC = 4.5 V to 5.5 V
pin E
-
-
-
60
50
3.5
216
180
-
µA
µA
pF
pin Sn
CI
input capacitance
Tamb = −40 °C to +85 °C
VIH
VIL
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
LOW-level input voltage
input leakage current
VCC = 4.5 V to 5.5 V
-
-
0.8
±1.0
V
II
VI = VCC or GND; VCC = 5.5 V
µA
IS(OFF)
OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 10
per channel
all channels
-
-
-
-
±1.0
±8.0
µA
µA
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
12 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
Table 8.
Static characteristics 74HCT4067 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol
IS(ON)
Parameter
Conditions
Min
Typ
Max
Unit
ON-state leakage current
VCC = 5.5 V; VI = VIH or VIL;
-
-
±8.0
µA
|VSW| = VCC − GND; see Figure 11
ICC
supply current
VI = VCC or GND; Vis = GND or VCC
;
-
-
80.0
µA
Vos = VCC or GND; VCC = 4.5 V to 5.5 V
∆ICC
additional supply current
per input pin; VI = VCC − 2.1 V; other
inputs at VCC or GND; VCC = 4.5 V to 5.5 V
pin E
-
-
-
-
270
225
µA
µA
pin Sn
Tamb = −40 °C to +125 °C
VIH
VIL
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
LOW-level input voltage
input leakage current
VCC = 4.5 V to 5.5 V
-
-
0.8
±1.0
V
II
VI = VCC or GND; VCC = 5.5 V
µA
IS(OFF)
OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 10
per channel
all channels
-
-
-
-
-
-
±1.0
±8.0
±8.0
µA
µA
µA
IS(ON)
ICC
ON-state leakage current
supply current
VCC = 5.5 V; VI = VIH or VIL;
|VSW| = VCC − GND; see Figure 11
VI = VCC or GND; Vis = GND or VCC
;
-
-
160
µA
Vos = VCC or GND; VCC = 4.5 V to 5.5 V
∆ICC
additional supply current
per input pin; VI = VCC − 2.1 V; other
inputs at VCC or GND; VCC = 4.5 V to 5.5 V
pin E
-
-
-
-
294
245
µA
µA
pin Sn
V
V
CC
CC
E
E
Z
V
V
IH
IL
I
Yn
Z
Yn
V
I
I
SW
os
SW
SW
GND
V
V
V
is
is
os
GND
001aag734
001aag735
Vis = VCC and Vos = GND
Vis = GND and Vos = VCC
Vis = VCC and Vos = open
Vis = GND and Vos = open
Fig 10. Test circuit for measuring OFF-state leakage
current
Fig 11. Test circuit for measuring ON-state leakage
current
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
13 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
Table 9.
Dynamic characteristics 74HC4067
GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C Unit
Max Max
(85 °C) (125 °C)
Typ
Max
[1][2]
tpd
propagation delay
Yn to Z; see Figure 12
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
Z to Yn
25
9
75
15
13
9
95
19
16
11
110
22
ns
ns
ns
ns
7
19
5
14
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
E to Yn; see Figure 13
VCC = 2.0 V
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
VCC = 9.0 V
Sn to Yn
18
6
60
12
10
8
75
15
13
10
90
18
15
12
ns
ns
ns
ns
5
4
[3]
toff
turn-off time
74
27
27
22
20
250
50
-
315
63
-
375
75
-
ns
ns
ns
ns
ns
43
38
54
48
64
57
VCC = 2.0 V
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
VCC = 9.0 V
E to Z
83
30
29
24
21
250
50
-
315
63
-
375
75
-
ns
ns
ns
ns
ns
43
38
54
48
64
57
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
Sn to Z
85
31
25
24
275
55
345
69
415
83
ns
ns
ns
ns
47
59
71
42
53
63
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
94
34
27
25
290
58
365
73
435
87
ns
ns
ns
ns
47
62
74
45
56
68
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
14 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
Table 9.
Dynamic characteristics 74HC4067 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C Unit
Max Max
(85 °C) (125 °C)
Typ
Max
[4]
ton
turn-on time
E to Yn; see Figure 13
VCC = 2.0 V
80
29
26
23
17
275
55
-
345
69
-
415
83
-
ns
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
47
42
59
53
71
63
VCC = 9.0 V
Sn to Yn
VCC = 2.0 V
88
32
29
26
18
300
60
-
375
75
-
450
90
-
ns
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
51
45
64
56
77
68
VCC = 9.0 V
E to Z
VCC = 2.0 V
85
31
25
18
275
55
345
69
415
83
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
47
59
71
VCC = 9.0 V
42
53
63
Sn to Z
VCC = 2.0 V
94
34
27
19
-
300
60
51
45
29
375
75
64
56
-
450
90
77
68
-
ns
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
[5]
CPD
power dissipation
capacitance
per switch; VI = GND to VCC
[1] tpd is the same as tPHL and tPLH
[2] Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal.
[3] ton is the same as tPHZ and tPLZ
[4] toff is the same as tPZH and tPZL
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑{(CL + Csw) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑{(CL + Csw) × VCC2 × fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
15 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
Table 10. Dynamic characteristics 74HCT4067
GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C Unit
Max Max
(85 °C) (125 °C)
Typ
Max
[1][2]
tpd
propagation delay
turn-off time
Yn to Z; see Figure 12
VCC = 4.5 V
9
6
15
12
19
15
22
18
ns
ns
Z to Yn
VCC = 4.5 V
[3]
toff
E to Yn; see Figure 13
VCC = 4.5 V
26
26
55
-
69
-
83
-
ns
ns
VCC = 5.0 V; CL = 15 pF
Sn to Yn
VCC = 4.5 V
31
30
55
-
69
-
83
-
ns
ns
VCC = 5.0 V; CL = 15 pF
E to Z
VCC = 4.5 V
30
35
60
60
75
75
90
90
ns
ns
Sn to Z
VCC = 4.5 V
[4]
ton
turn-on time
E to Yn; see Figure 13
VCC = 4.5 V
32
32
60
-
75
-
90
-
ns
ns
VCC = 5.0 V; CL = 15 pF
Sn to Yn
VCC = 4.5 V
35
33
60
-
75
-
90
-
ns
ns
VCC = 5.0 V; CL = 15 pF
E to Z
VCC = 4.5 V
38
65
81
98
ns
Sn to Z
VCC = 4.5 V
38
-
65
29
81
-
98
-
ns
[5]
CPD
power dissipation
capacitance
per switch; VI = GND to (VCC − 1.5 V)
pF
[1] tpd is the same as tPHL and tPLH
.
[2] Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal.
[3] ton is the same as tPHZ and tPLZ
[4] toff is the same as tPZH and tPZL
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑{(CL + Csw) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑{(CL + Csw) × VCC2 × fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
16 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
12. Waveforms
50 %
V
input
is
t
t
PLH
PHL
50 %
V
output
os
001aad555
Fig 12. Input (Vis) to output (Vos) propagation delays
V
I
V
E, Sn inputs
0 V
M
t
t
PZL
PLZ
50 %
V
V
output
output
os
10 %
t
t
PHZ
PZH
90 %
50 %
os
switch ON
switch OFF
switch ON
001aad556
Measurement points are shown in Table 11.
Fig 13. Turn-on and turn-off times
Table 11. Measurement points
Type
VI
VM
74HC4067
74HCT4067
VCC
3.0 V
0.5VCC
1.3 V
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
17 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
V
CC
CC
is
V
V
os
I
S1
R
L
PULSE
GENERATOR
open
DUT
R
T
C
L
GND
001aag732
Test data is given in Table 12.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistor.
S1 = Test selection switch.
Fig 14. Load circuitry for measuring switching times
Table 12. Test data
Test
Input
Output
Switch Z (Yn)
CL
S1 position
Control E
VI[1]
Address Sn
VI[1]
Switch Yn (Z) tr, tf
Vis
RL
tPHL, tPLH
tPHZ, tPZH
tPLZ, tPZL
GND
GND or VCC
GND to VCC
GND to VCC
GND to VCC
VCC
6 ns
6 ns
6 ns
50 pF
-
open
GND
VCC
GND to VCC
GND to VCC
50 pF, 15 pF 1 kΩ
50 pF, 15 pF 1 kΩ
GND
[1] For 74HCT4067: maximum input voltage VI = 3.0 V.
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
18 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
13. Additional dynamic characteristics
Table 13. Additional dynamic characteristics
Recommended conditions and typical values; GND = 0 V; Tamb = 25 °C.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
os is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
V
Symbol Parameter
Conditions
Min
Typ
Max
Unit
THD
total harmonic distortion
RL = 10 kΩ; CL = 50 pF; see Figure 15
fi = 1 kHz
VCC = 4.5 V; Vis(p-p) = 4.0 V
VCC = 9.0 V; Vis(p-p) = 8.0 V
fi = 10 kHz
-
-
0.04
0.02
-
-
%
%
VCC = 4.5 V; Vis(p-p) = 4.0 V
VCC = 9.0 V; Vis(p-p) = 8.0 V
RL = 600 Ω; CL = 50 pF; see Figure 16
VCC = 4.5 V
-
-
0.12
0.06
-
-
%
%
[1]
[2]
αiso
isolation (OFF-state)
-
-
−50
−50
-
-
dB
dB
VCC = 9.0 V
f(-3dB)
−3 dB frequency response RL = 50 Ω; CL = 10 pF; see Figure 17
VCC = 4.5 V
VCC = 9.0 V
-
-
-
-
90
100
5
-
-
-
-
MHz
MHz
pF
Csw
switch capacitance
independent pins Y
common pin Z
45
pF
[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω).
[2] Adjust input voltage Vis to 0 dBm level at Vos for fi = 1 MHz (0 dBm = 1 mW into 50 Ω). After set-up, fi is increased to obtain a reading of
−3 dB at Vos
.
V
V
CC
CC
E
2R
L
V
V
IL
10 µF
Yn
Z
is
V
os
GND
f
2R
L
C
L
D
i
001aag736
Fig 15. Test circuit for measuring total harmonic distortion
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
19 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
001aae332
0
α
iso
(dB)
−20
−40
−60
−80
−100
2
3
4
5
6
10
10
10
10
10
10
f (kHz)
i
a. Isolation (OFF-state)
V
V
CC
CC
E
2R
L
V
IH
0.1 µF
V
Yn
Z
is
V
os
GND
f
2R
L
C
L
dB
i
001aag737
b. Test circuit
VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.
Fig 16. Isolation (OFF-state) as a function of frequency
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
20 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
001aag739
5
0
V
os
(dB)
−5
2
3
4
5
6
10
10
10
10
10
10
f (kHz)
i
a. Typical −3 dB frequency response
V
V
CC
CC
E
Yn
2R
L
V
V
IL
0.1 µF
Z
is
V
os
GND
f
2R
L
C
L
dB
i
001aag738
b. Test circuit
VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.
Fig 17. −3 dB frequency response
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
21 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
14. Package outline
DIP24: plastic dual in-line package; 24 leads (600 mil)
SOT101-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.7
1.3
0.53
0.38
0.32
0.23
32.0
31.4
14.1
13.7
3.9
3.4
15.80
15.24
17.15
15.90
5.1
0.2
0.51
4
2.54
0.1
15.24
0.6
0.25
0.01
2.2
0.066
0.051
0.021
0.015
0.013
0.009
1.26
1.24
0.56
0.54
0.15
0.13
0.62
0.60
0.68
0.63
inches
0.02
0.16
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT101-1
051G02
MO-015
SC-509-24
Fig 18. Package outline SOT101-1 (DIP24)
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
22 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 19. Package outline SOT137-1 (SO24)
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
23 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
v
c
H
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT340-1
MO-150
Fig 20. Package outline SOT340-1 (SSOP24)
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
24 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 21. Package outline SOT355-1 (TSSOP24)
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
25 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
SOT815-1
D
B
A
A
A
E
1
c
detail X
terminal 1
index area
C
e
1
terminal 1
index area
y
y
v
M
C
C
A B
C
1
e
b
w
M
2
11
L
12
13
1
e
E
h
2
24
23
14
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
D
D
E
E
h
e
e
e
L
v
w
y
y
1
1
2
1
h
max.
0.05 0.30
0.00 0.18
5.6
5.4
4.25
3.95
3.6
3.4
2.25
1.95
0.5
0.3
mm
1
0.2
0.5
4.5
1.5
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-04-29
SOT815-1
- - -
- - -
- - -
Fig 22. Package outline SOT815-1 (DHVQFN24)
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
26 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
15. Revision history
Table 14. Revision history
Document ID
Release date
20071015
Data sheet status
Change notice
Supersedes
74HC_HCT4067_3
Modifications:
Product data sheet
-
74HC_HCT4067_CNV_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added: type numbers 74HC4067BQ and 74HCT4067BQ (DHVQFN24 package).
74HC_HCT4067_CNV_2 19970901
Product specification
-
-
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
27 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
16.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
28 of 29
74HC4067; 74HCT4067
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
Functional description . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 14
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Additional dynamic characteristics . . . . . . . . 19
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 28
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 28
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 October 2007
Document identifier: 74HC_HCT4067_3
相关型号：
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