74HC573D-Q100_技术文档

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

Rev. 2 — 16 August 2012

Product data sheet

1. General description

The 74HC573-Q100; 74HCT573-Q100 is a high-speed Si-gate CMOS device and is pin

compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard no. 7A.

The 74HC573-Q100; 74HCT573-Q100 has octal D-type transparent latches featuring

separate D-type inputs for each latch and 3-state true outputs for bus-oriented

applications. A latch enable (LE) input and an output enable (OE) input are common to all

latches.

When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are

transparent, i.e. a latch output changes state each time its corresponding D input

changes.

When LE is LOW the latches store the information that was present at the D-inputs a

set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents

of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the

high-impedance OFF-state. Operation of the OE input does not affect the state of the

latches.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Input levels:

 For 74HC573: CMOS level

 For 74HCT573: TTL level

 Inputs and outputs on opposite sides of package allowing easy interface with

microprocessors

 Useful as input or output port for microprocessors and microcomputers

 3-state non-inverting outputs for bus-oriented applications

 Common 3-state output enable input

 Multiple package options

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature

range

Name

Description

Version

74HC573D-Q100

74HCT573D-Q100

40 C to +125 C SO20

plastic small outline package; 20 leads;

body width 7.5 mm

SOT163-1

74HC573PW-Q100 40 C to +125 C TSSOP20

plastic thin shrink small outline package; 20 leads;

body width 4.4 mm

SOT360-1

74HCT573PW-Q100

74HC573BQ-Q100 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1

thin quad flat package; no leads; 20 terminals;

body 2.5  4.5  0.85 mm

74HCT573BQ-Q100

4. Functional diagram

2

3

4

5

6

7

8

9

D0

D1

D2

D3

D4

D5

D6

D7

19

Q0

Q1 18

17

16

15

14

13

12

Q2

Q3

LATCH

1 to 8

3-STATE

OUTPUTS Q4

Q5

Q6

Q7

LE

11

1

OE

mna809

Fig 1. Functional diagram

74HC_HCT573_Q100

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Product data sheet

Rev. 2 — 16 August 2012

2 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

D0

D1

D2

D3

D4

D5

D6

D7

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

LATCH

1

LATCH

2

LATCH

3

LATCH

4

LATCH

5

LATCH

6

LATCH

7

LATCH

8

LE

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

001aae075

Fig 2. Logic diagram

11

C1

1

EN1

1

2

19

1D

OE

2

19

18

17

16

15

14

13

12

D0

Q0

3

4

5

18

17

16

3

4

5

6

7

8

9

D1

D2

D3

D4

D5

D6

D7

Q1

Q2

Q3

Q4

Q5

Q6

Q7

6

7

8

9

15

14

13

12

LE

11

mna807

mna808

Fig 3. Logic symbol

Fig 4. IEC logic symbol

74HC_HCT573_Q100

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Product data sheet

Rev. 2 — 16 August 2012

3 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

5. Pinning information

5.1 Pinning

74HC573-Q100

74HCT573-Q100

terminal 1

index area

74HC573-Q100

74HCT573-Q100

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

1

2

20

19

18

17

16

15

14

13

12

11

OE

D0

V

CC

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

LE

3

D1

4

D2

5

D3

6

GND(1)

D4

7

D5

8

D6

9

D7

aaa-003604

10

GND

Transparent top view

aaa-003603

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as

supply pin or input

Fig 5. Pin configuration SO20 and TSSOP20

Fig 6. Pin configuration DHVQFN20

5.2 Pin description

Table 2.

Symbol

OE

Pin description

Description

1

3-state output enable input (active LOW)

data input

D[0:7]

GND

LE

2, 3, 4, 5, 6, 7, 8, 9

10

11

ground (0 V)

latch enable input (active HIGH)

Q[0:7]

V_CC

19, 18, 17, 16, 15, 14, 13, 12 3-state latch output

20

supply voltage

74HC_HCT573_Q100

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Product data sheet

Rev. 2 — 16 August 2012

4 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

6. Functional description

Table 3.

Function table^[1]

Operating mode

Control

Input

Internal

latches

Output

OE

LE

Dn

L

H

l

Qn

L

Enable and read register (transparent

mode)

L

H

L

H

L

H

L

Latch and read register

L

h

l

H

L

H

Z

Latch register and disable outputs

H

h

H

Z

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;

Z = high-impedance OFF-state.

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7

Unit

V

supply voltage

0.5

input clamping current

output clamping current

output current

V_I< 0.5 V or V_I> V_CC+ 0.5 V

V_O< 0.5 V or V_O> V_CC+ 0.5 V

V_O= 0.5 V to (V_CC+ 0.5 V)

-

20

35

+70

70

+150

750

500

mA

C

I_OK

-

I_O

-

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

-

storage temperature

total power dissipation

65

[1]

[2]

DIP20 package

-

mW

SO20, SSOP20, TSSOP20 and

DHVQFN20 packages

[1] For DIP20 package: P_totderates linearly with 12 mW/K above 70 C.

[2] For SO20: P_totderates linearly with 8 mW/K above 70 C.

For SSOP20 and TSSOP20 packages: P_totderates linearly with 5.5 mW/K above 60 C.

For DHVQFN20 package: P_totderates linearly with 4.5 mW/K above 60 C.

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 August 2012

5 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions

74HC573-Q100

74HCT573-Q100

Unit

Min

Typ

Max

6.0

Min

Typ

Max

5.5

V_CC

+125

-

V_CC

V_I

supply voltage

2.0

5.0

4.5

5.0

V

input voltage

0

-

V_CC

+125

625

139

83

0

-

V

V_O

output voltage

0

-

0

-

V

T_amb

t/V

ambient temperature

input transition rise and fall rate V_CC= 2.0 V

V_CC= 4.5 V

40

+25

40

+25

C

-

ns/V

1.67

-

1.67

-

139

-

V_CC= 6.0 V

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 C

Min Typ

40 C to +85 C 40 C to +125 C Unit

Max

Min

Max

Min

Max

74HC573-Q100

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

1.5

1.2

2.4

3.2

0.8

-

1.5

-

1.5

-

V

V_CC= 4.5 V

3.15

V_CC= 6.0 V

4.2

-

4.2

-

4.2

-

V_IL

LOW-level

input voltage

V_CC= 2.0 V

-

0.5

-

0.5

1.35

1.8

-

0.5

1.35

1.8

V_CC= 4.5 V

2.1 1.35

V_CC= 6.0 V

2.8

1.8

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

1.9

4.4

5.9

2.0

4.5

6.0

-

1.9

4.4

-

1.9

4.4

5.9

3.7

5.2

-

V

5.9

I_O= 6.0 mA; V_CC= 4.5 V 3.98 4.32

I_O= 7.8 mA; V_CC= 6.0 V 5.48 5.81

V_I= V_IHor V_IL

3.84

5.34

V_OL

LOW-level

output voltage

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

I_O= 6.0 mA; V_CC= 4.5 V

I_O= 7.8 mA; V_CC= 6.0 V

-

0

0.1

-

0.1

-

0.1

0.4

1.0

V

0.1

V

0.15 0.26

0.16 0.26

0.33

1.0

V

I_I

input leakage

current

V_I= V_CCor GND;

V_CC= 6.0 V

-

0.1

A

I_OZ

OFF-state

V_I= V_IHor V_IL;

-

0.5

-

5.0

-

10.0 A

output current V_O= V_CCor GND;

V_CC= 6.0 V

74HC_HCT573_Q100

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Product data sheet

Rev. 2 — 16 August 2012

6 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

Table 6.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ

Max

Min

Max

Min

Max

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

-

8.0

-

80

-

160

A

C_I

input

-

3.5

-

pF

capacitance

74HCT573-Q100

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

1.6

1.2

-

2.0

-

2.0

-

V

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 A

4.4

4.5

-

4.4

-

4.4

3.7

-

V

I_O= 6 mA

3.98 4.32

3.84

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 A

-

0

0.1

-

0.1

-

0.1

0.4

V

I_O= 6.0 mA

0.16 0.26

0.33

1.0

V

I_I

input leakage

current

V_I= V_CCor GND;

V_CC= 5.5 V

-

0.1

1.0

A

I_OZ

OFF-state

V_I= V_IHor V_IL; V_CC= 5.5 V;

-

0.5

-

5.0

-

10

A

output current V_O= V_CCor GND per input

pin; other inputs at V_CCor

GND; I_O= 0 A

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

-

8.0

-

80

-

160

I_CC

additional

V_I= V_CC 2.1 V;

supply current other inputs at V_CCor GND;

V_CC= 4.5 V to 5.5 V;

I_O= 0 A

per input pin; Dn inputs

per input pin; LE input

per input pin; OE input

-

35

65

126

234

450

-

158

293

563

-

172

319

613

A

pF

125

3.5

C_I

input

capacitance

74HC_HCT573_Q100

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Product data sheet

Rev. 2 — 16 August 2012

7 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit see Figure 11.

Symbol Parameter Conditions

For type 74HC573-Q100

25 C

40 C to +85 C 40 C to +125 C Unit

Min

Typ Max Min

Max

Min

Max

[1]

t_pd

propagation Dn to Qn; see Figure 7

delay

V_CC= 2.0 V

-

47

17

14

150

30

-

190

38

-

225

45

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

26

33

38

[1]

t_pd

propagation LE to Qn; see Figure 8

delay

V_CC= 2.0 V

-

50

18

15

14

150

30

-

190

38

-

225

45

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

26

33

38

[2]

[3]

[4]

t_en

t_dis

t_t

enable time OE to Qn; see Figure 9

V_CC= 2.0 V

-

44

16

13

140

28

-

175

35

-

210

42

ns

V_CC= 4.5 V

V_CC= 6.0 V

24

30

36

disable time OE to Qn; see Figure 9

V_CC= 2.0 V

-

55

20

16

150

30

-

190

38

-

225

45

ns

V_CC= 4.5 V

V_CC= 6.0 V

26

33

38

transition

time

Qn; see Figure 7

V_CC= 2.0 V

-

14

5

60

12

10

-

75

15

13

-

90

18

15

ns

V_CC= 4.5 V

V_CC= 6.0 V

4

t_W

t_su

t_h

pulse width LE HIGH; see Figure 8

V_CC= 2.0 V

80

16

14

5

-

100

20

-

120

24

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

4

17

20

set-up time Dn to LE; see Figure 10

V_CC= 2.0 V

50

10

9

11

4

-

65

13

11

-

75

15

13

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

3

hold time

Dn to LE; see Figure 10

V_CC= 2.0 V

5

-

3

1

-

5

-

5

-

ns

pF

V_CC= 4.5 V

V_CC= 6.0 V

1

[5]

C_PD

power

dissipation

capacitance

C_L= 50 pF; f = 1 MHz;

V_I= GND to V_CC

26

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 August 2012

8 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit see Figure 11.

Symbol Parameter Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min

Typ Max Min

Max

Min

Max

For type 74HCT573-Q100

[1]

t_pd

propagation Dn to Qn; see Figure 7

delay

V_CC= 4.5 V

-

20

17

35

-

44

-

53

-

ns

V_CC= 5 V; C_L= 15 pF

t_pd

propagation LE to Qn; see Figure 8

delay

V_CC= 4.5 V

-

18

15

35

-

44

-

53

-

ns

V_CC= 5 V; C_L= 15 pF

enable time OE to Qn; see Figure 9

V_CC= 4.5 V

[2]

[3]

[4]

t_en

t_dis

t_t

-

17

18

5

30

12

-

38

15

-

45

18

-

ns

disable time OE to Qn; see Figure 9

V_CC= 4.5 V

transition

time

Qn; see Figure 7

V_CC= 4.5 V

-

t_W

t_su

t_h

pulse width LE HIGH; see Figure 8

V_CC= 4.5 V

16

13

5

20

16

24

20

set-up time Dn to LE; see Figure 10

V_CC= 4.5 V

7

-

hold time

Dn to LE; see Figure 10

V_CC= 4.5 V

9

-

4

-

11

-

15

-

ns

[5]

C_PD

power

dissipation

capacitance

C_L= 50 pF; f = 1 MHz;

V_I= GND to V_CC

26

pF

[1] t_pdis the same as t_PLHand t_PHL

[2] t_enis the same as t_PZHand t_PZL

[3] t_disis the same as t_PLZand t_PHZ

[4] t_tis the same as t_THLand t_TLH

.

[5] C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

(C_L V_CC² f_o) = sum of outputs.

74HC_HCT573_Q100

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Product data sheet

Rev. 2 — 16 August 2012

9 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

11. Waveforms

Dn input

V

M

t

PHL

PLH

90 %

V

Qn output

M

10 %

TLH

t

THL

001aae082

Measurement points are given in Table 8.

Fig 7. Propagation delay data input (Dn) to output (Qn) and output transition time

LE input

V

M

t

W

t

PHL

PLH

90 %

Qn output

V

M

10 %

t

TLH

THL

001aae083

Measurement points are given in Table 8.

Fig 8. Pulse width latch enable input (LE), propagation delay latch enable input (LE) to output (Qn) and output

transition time

74HC_HCT573_Q100

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Product data sheet

Rev. 2 — 16 August 2012

10 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

V

I

OE input

output

V

M

GND

t

PZL

PLZ

V

CC

V

LOW-to-OFF

OFF-to-LOW

M

10%

V

OL

t

PZH

PHZ

V

OH

90%

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aae307

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 9. Enable and disable times

V

h

LE input

M

t

su

t

h

V

Dn input

M

001aae084

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 10. Set-up and hold times for data input (Dn) to latch input (LE)

Table 8.

Type

Measurement points

Input

V_M

Output

V_M

74HC573-Q100

74HCT573-Q100

0.5V_CC

1.3 V

0.5V_CC

1.3 V

74HC_HCT573_Q100

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Product data sheet

Rev. 2 — 16 August 2012

11 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

CC

V

O

I

R

L

S1

G

open

DUT

R

T

C

L

001aad983

Test data is given in Table 9.

Definitions test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

R_L= Load resistance.

S1 = Test selection switch.

Fig 11. Test circuit for measuring switching times

Table 9.

Type

Test data

Input

Load

S1 position

t_PHL, t_PLH

open

V_I

t_r, t_f

6 ns

C_L

R_L

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

V_CC

74HC573-Q100

V_CC

15 pF, 50 pF

1 k

74HCT573-Q100 3 V

open

GND

V_CC

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 August 2012

12 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

12. Package outline

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig 12. Package outline SOT163-1 (SO20)

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 August 2012

13 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig 13. Package outline SOT360-1 (TSSOP20)

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 August 2012

14 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

SOT764-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

9

L

1

10

E

h

e

20

11

19

12

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

1

y

D

E

L

v

w

y

1

h

max.

0.05 0.30

0.00 0.18

4.6

4.4

3.15

2.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT764-1

- - -

MO-241

- - -

Fig 14. Package outline SOT764-1 (DHVQFN20)

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 August 2012

15 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

13. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

ESD

Description

Complementary Metal Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

TTL

Transistor-Transistor Logic

Military

MIL

14. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

20120816 Product data sheet

Change notice

Supersedes

74HC_HCT573_Q100 v.2

Modifications:

-

74HC_HCT573_Q100 v.1

• Alternative descriptive title corrected (errata).

20120802 Product data sheet

74HC_HCT573_Q100 v.1

-

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 August 2012

16 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

15.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 August 2012

17 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 16 August 2012

18 of 19

74HC573-Q100; 74HCT573-Q100

NXP Semiconductors

Octal D-type transparent latch; 3-state

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 August 2012

Document identifier: 74HC_HCT573_Q100


型号：	74HC573D-Q100
厂家：	NXP
描述：	Octal D-type transparent latch; 3-state 八路D型透明锁存器;三态锁存器逻辑集成电路光电二极管驱动
文件：	总19页 (文件大小：253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HC573D-Q100 [NXP]

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