74HC58DB,118 [NXP]
74HC58 - Dual AND-OR gate SSOP1 14-Pin;
| 型号： | 74HC58DB,118 |
| 厂家： | 
NXP |
| 描述： | 74HC58 - Dual AND-OR gate SSOP1 14-Pin |
| 文件： | 总5页 (文件大小：35K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC58
Dual AND-OR gate
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Dual AND-OR gate
74HC58
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and
the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 15 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PHL/ tPLH
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
t
CL = 15 pF; VCC = 5 V
1n to 1Y
11
9
ns
ns
pF
2n to 2Y
CI
input capacitance
3.5
CPD
power dissipation capacitance per
gate
notes 1 and 2
18
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
2. For HC the condition is VI = GND to VCC
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Dual AND-OR gate
74HC58
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
data inputs
1, 12, 13, 9, 10, 11
1A to 1F
2A to 2D
1Y, 2Y
GND
2, 3, 4, 5
data inputs
8, 6
7
data outputs
ground (0 V)
14
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual AND-OR gate
74HC58
Fig.4 Functional diagram.
Fig.5 Logic diagram.
FUNCTION TABLE (1)
INPUTS
INPUTS
2B 2C
OUTPUT
2Y
OUTPUT
1Y
2A
2D
1A
1B
1C
1D
1E
1F
L
L
X
X
X
H
X
X
L
L
X
H
L
X
L
X
H
X
X
L
X
L
H
X
L
L
L
L
H
H
L
X
X
L
X
X
X
L
X
X
L
L
L
L
L
L
L
X
X
X
X
L
L
X
X
X
X
X
X
L
L
X
X
L
X
X
X
X
X
X
H
L
X
L
L
L
X
H
X
L
X
X
H
X
X
X
L
X
H
X
L
L
L
L
L
H
H
X
X
X
X
H
X
X
L
H
X
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
December 1990
4
Philips Semiconductors
Product specification
Dual AND-OR gate
74HC58
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH
propagation delay
1A,1B,1C,1D,1E,
1F to 1Y
36
13
10
115
23
20
145
29
25
175
35
30
ns
2.0
4.5
6.0
Fig.6
Fig.6
Fig.6
t
t
PHL/ tPLH
propagation delay
2A,2B,2C,2D to 2Y
30
11
9
100
20
17
125
25
21
150
30
26
ns
ns
2.0
4.5
6.0
THL/ tTLH
output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
AC WAVEFORMS
(1)
nA, nB, nC, nD,
1E, 1F INPUT
V
M
t
t
PHL
PLH
(1)
V
M
nY OUTPUT
t
t
MBA336
(1) HC : VM = 50%; VI = GND to VCC
.
THL
TLH
Fig.6 Waveforms showing the input (nA, nB, nC, nD, 1E, 1F) to output (nY) propagation delays and the output
transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
5
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