74HC75DB,118 [NXP]
74HC75 - Quad bistable transparent latch SSOP1 16-Pin;
| 型号： | 74HC75DB,118 |
| 厂家： | 
NXP |
| 描述： | 74HC75 - Quad bistable transparent latch SSOP1 16-Pin 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC75
Quad bistable transparant latch
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC
standard no. 7A.
The 74HC75 has four bistable latches. The two latches are simultaneously controlled by
one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data
enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs
(nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time
prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched
outputs remain stable as long as the LEnn is LOW.
2. Features
■ Complementary Q and Q outputs
■ VCC and GND on the center pins
■ Low-power dissipation
■ Complies with JEDEC standard no. 7A
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Multiple package options
■ Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
74HC75
Philips Semiconductors
Quad bistable transparant latch
3. Quick reference data
Table 1:
Symbol
tPHL, tPLH
Quick reference data
Parameter
Conditions
Min
Typ
Max
Unit
propagation delay
CL = 15 pF;
VCC = 5 V
nD to nQ, nQ
LEnn to nQ, nQ
input capacitance
-
-
-
-
11
11
3.5
42
-
-
-
-
ns
ns
pF
pF
CI
[1]
CPD
power dissipation
VI = GND to VCC
capacitance per latch
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range
−40 °C to +125 °C
−40 °C to +125 °C
Name
DIP16
SO16
Description
Version
74HC75N
74HC75D
plastic dual in-line package; 16 leads (300 mil) SOT38-4
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC75DB
74HC75PW
−40 °C to +125 °C
−40 °C to +125 °C
SSOP16
plastic shrink small outline package; 16 leads; SOT338-1
body width 5.3 mm
TSSOP16
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT403-1
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
2 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
5. Functional diagram
1D
1Q
1Q
2
D
Q
Q
Q
Q
16
1
LE12
13
CP
L1
L2
L3
L4
13
2D
2Q
2Q
3
D
15
14
LE12
16
1Q
2
1D
1
CP
1Q
15
2Q
3
2D
14
2Q
L1,2
L3,4
3D
3Q
3Q
10
11
9
6
4
D
10
11
3Q
3Q
4Q
4Q
6
7
3D
4D
LE34
CP
8
LE34
4
001aab851
4D
4Q
4Q
7
D
9
8
CP
001aab853
Fig 1. Functional diagram
Fig 2. Logic symbol
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
3 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
1D
D
Q
Q
Q
Q
1Q
1Q
LE12
CP
LATCH
1
13
C1
1D
16
1
2D
D
2Q
2Q
2
3
CP
15
14
LATCH
2
4
C1
1D
3D
D
3Q
3Q
9
7
6
LE34
CP
LATCH
8
10
11
3
001aab852
4D
D
4Q
4Q
CP
LATCH
4
001aab854
Fig 3. IEC logic symbol
Fig 4. Logic diagram
6. Pinning information
6.1 Pinning
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1Q
1D
2D
1Q
2Q
2Q
LE34
LE12
GND
3Q
75
V
CC
3D
4D
4Q
3Q
4Q
001aab850
Fig 5. Pin configuration
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
4 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
6.2 Pin description
Table 3:
Symbol
1Q
Pin description
Pin
1
Description
complementary latch output 1
data input 1
1D
2
2D
3
data input 2
LE34
VCC
3D
4
latch enable input for latches 3 and 4 (active HIGH)
positive supply voltage
data input 3
5
6
4D
7
data input 4
4Q
8
complementary latch output 4
latch output 4
4Q
9
3Q
10
11
12
13
14
15
16
latch output 3
3Q
complementary latch output 3
ground (0 V)
GND
LE12
2Q
latch enable input for latches 1 and 2 (active HIGH)
complementary latch output 2
latch output 2
2Q
1Q
latch output 1
7. Functional description
7.1 Function table
Table 4:
Function table[1]
Operating mode Input
LEnn
Output
nD
L
nQ
L
nQ
H
Data enabled
H
H
L
H
H
L
Data latched
X
q
q
[1] H = HIGH voltage level;
L = LOW voltage level;
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW
LEnn transition;
X = don’t care.
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
5 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max Unit
VCC
IIK
supply voltage
−0.5 +7
V
input diode current
output diode current
VI < −0.5 V or VI > VCC + 0.5 V
-
-
±20
mA
mA
IOK
VO < −0.5 V or
VO > VCC + 0.5 V
±20
±25
±50
IO
output source or sink
current
VO = −0.5 V to VCC + 0.5 V
-
mA
ICC, IGND VCC or GND current
-
mA
Tstg
Ptot
storage temperature
power dissipation
DIP16 package
−65
+150 °C
[1]
[2]
-
-
750
500
mW
SO16, SSOP16 and
TSSOP16 packages
mW
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 6:
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
V
supply voltage
input voltage
output voltage
2.0
5.0
6.0
VI
0
-
VCC
VCC
1000
500
400
+125
V
VO
0
-
V
tr, tf
input rise and fall
times
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
ns
ns
ns
°C
-
6.0
-
-
-
Tamb
ambient
−40
temperature
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
6 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
10. Static characteristics
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 °C
VIH
Parameter
Conditions
Min
Typ
Max
Unit
HIGH-level input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-level input voltage
HIGH-level output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
2.0
-
-
-
-
-
V
V
V
V
V
4.4
4.5
5.9
6.0
3.98
5.48
4.32
5.81
VOL
LOW-level output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VCC or GND; IO = 0 A;
-
-
-
-
-
-
-
0
0.1
V
0
0.1
V
0
0.1
V
0.15
0.26
0.26
±0.1
8.0
V
0.16
V
ILI
input leakage current
-
-
µA
µA
ICC
quiescent supply current
VCC = 6.0 V
CI
input capacitance
-
3.5
-
pF
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-level input voltage
HIGH-level output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
1.9
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
4.4
5.9
3.84
5.34
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
7 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VCC or GND; IO = 0 A;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.1
V
0.1
V
0.33
0.33
±1.0
80
V
V
ILI
input leakage current
µA
µA
ICC
quiescent supply current
VCC = 6.0 V
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-level input voltage
HIGH-level output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VCC or GND; IO = 0 A;
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
160
V
V
V
V
V
ILI
input leakage current
µA
µA
ICC
quiescent supply current
VCC = 6.0 V
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
8 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
11. Dynamic characteristics
Table 8:
Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specified, see Figure 10.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL, tPLH
propagation delay
nD to nQ
see Figure 6
VCC = 2.0 V
-
-
-
-
33
12
10
11
110
22
19
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
see Figure 7
propagation delay
nD to nQ
VCC = 2.0 V
-
-
-
-
39
14
11
11
120
24
20
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
see Figure 9
propagation delay
LEnn to nQ
VCC = 2.0 V
-
-
-
-
33
12
10
11
120
24
20
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
see Figure 9
propagation delay
LEnn to nQ
VCC = 2.0 V
-
-
-
-
39
14
11
11
125
25
21
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
tTHL, tTLH
output transition time see Figure 6 and 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
19
7
75
15
13
ns
ns
ns
6
tW
tsu
th
enable pulse width
HIGH
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
17
6
-
-
-
ns
ns
ns
5
set-up time nD to
LEnn
60
12
10
14
5
-
-
-
ns
ns
ns
4
hold time nD to LEnn see Figure 8
VCC = 2.0 V
3
3
3
−8
−3
−2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
9 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specified, see Figure 10.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
CPD
power dissipation
VI = GND to VCC
-
42
-
pF
capacitance per latch
Tamb = −40 °C to +85 °C
tPHL, tPLH
propagation delay
nD to nQ
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
140
28
ns
ns
ns
24
propagation delay
nD to nQ
-
-
-
-
-
-
150
30
ns
ns
ns
26
propagation delay
LEnn to nQ
-
-
-
-
-
-
150
30
ns
ns
ns
26
propagation delay
LEnn to nQ
-
-
-
-
-
-
155
31
ns
ns
ns
26
tTHL, tTLH
output transition time see Figure 6 and 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
95
19
16
ns
ns
ns
tW
tsu
th
enable pulse width
HIGH
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
-
-
-
-
-
-
ns
ns
ns
17
set-up time nD to
LEnn
75
15
13
-
-
-
-
-
-
ns
ns
ns
hold time nD to LEnn see Figure 8
VCC = 2.0 V
3
3
3
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
10 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specified, see Figure 10.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
tPHL, tPLH
propagation delay
nD to nQ
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
165
33
ns
ns
ns
28
propagation delay
nD to nQ
-
-
-
-
-
-
180
36
ns
ns
ns
31
propagation delay
LEnn to nQ
-
-
-
-
-
-
180
36
ns
ns
ns
31
propagation delay
LEnn to nQ
-
-
-
-
-
-
190
38
ns
ns
ns
32
tTHL, tTLH
output transition time see Figure 6 and 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
110
22
ns
ns
ns
19
tW
tsu
th
enable pulse width
HIGH
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
120
24
-
-
-
-
-
-
ns
ns
ns
20
set-up time nD to
LEnn
90
18
15
-
-
-
-
-
-
ns
ns
ns
hold time nD to LEnn see Figure 8
VCC = 2.0 V
3
3
3
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
11 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
12. Waveforms
nD input
V
M
t
t
PLH
PHL
nQ output
V
M
t
t
THL
TLH
001aab855
VM = 0.5 × VI.
Fig 6. Waveforms showing the data input (nD) to output (nQ) propagation delays and the
output transition times
nD input
V
M
t
t
PLH
PHL
nQ output
V
M
t
t
THL
TLH
001aab856
VM = 0.5 × VI.
Fig 7. Waveforms showing the data input (nD) to output (nQ) propagation delays and the
output transition times
nD input
V
M
t
t
h
h
t
t
su
su
V
LEnn input
M
nQ output
Q = D
Q = D
001aab858
The shaded areas indicate when the input is permitted to change for predictable output
performance.
VM = 0.5 × VI.
Fig 8. Waveforms showing the data set-up and hold times for nD input to LEnn input
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
12 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
nD input
LEnn input
V
M
t
W
t
t
PLH
PHL
V
nQ output
nQ output
M
t
t
TLH
THL
t
t
PHL
PLH
V
M
t
t
TLH
THL
001aab857
VM = 0.5 × VI.
Fig 9. Waveforms showing the latch enable input (LEnn) pulse width, the latch enable
input to outputs (nQ, nQ) propagation delays and the output transition times
V
CC
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
L
R
T
mna101
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 10. Load circuitry for switching times
Table 9:
Supply
VCC
Test data
Input
VI
Load
CL
tr, tf
6 ns
6 ns
6 ns
6 ns
2.0 V
VCC
VCC
VCC
VCC
50 pF
50 pF
50 pF
15 pF
4.5 V
6.0 V
5.0 V
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
13 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 11. Package outline SOT38-4 (DIP16)
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
14 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 12. Package outline SOT109-1 (SO16)
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
15 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 13. Package outline SOT338-1 (SSOP16)
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
16 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 14. Package outline SOT403-1 (TSSOP16)
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
17 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
14. Revision history
Table 10: Revision history
Document ID
74HC75_3
Release date Data sheet status
20041112 Product data sheet
Change notice Doc. number
Supersedes
-
9397 750 13816 74HC_HCT75_CNV_2
Modifications:
• The format of this data sheet has been redesigned to comply with the current presentation and
information standard of Philips Semiconductors.
• Removed type number 74HCT75.
• Inserted family specification.
74HC_HCT75_CNV_2 19970918
Product specification
-
-
-
-
74HC_HCT75_1
-
74HC_HCT75_1
19901201
Product specification
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
18 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
19 of 20
74HC75
Philips Semiconductors
Quad bistable transparant latch
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information . . . . . . . . . . . . . . . . . . . . 19
9
10
11
12
13
14
15
16
17
18
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 12 November 2004
Document number: 9397 750 13816
Published in The Netherlands
相关型号：
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