74HC75NB [NXP]
HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16;
| 型号： | 74HC75NB |
| 厂家： | 
NXP |
| 描述： | HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 锁存器 |
| 文件： | 总7页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT75
Quad bistable transparent latch
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
The 74HC/HCT75 have four bistable latches. The two
latches are simultaneously controlled by one of two active
HIGH enable inputs (LE1-2 and LE3-4). When LEn-n is
HIGH, the data enters the latches and appears at the nQ
outputs. The nQ outputs follow the data inputs (nD) as long
as LEn-n is HIGH (transparent). The data on the nD inputs
one set-up time prior to the HIGH-to-LOW transition of the
LEn-n will be stored in the latches. The latched outputs
remain stable as long as the LEn-n is LOW.
FEATURES
• Complementary Q and Q outputs
• VCC and GND on the centre pins
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT75 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CL = 15 pF; VCC = 5 V
nD to nQ, nQ
11
12
ns
ns
LEn-n to nQ, nQ
11
11
CI
input capacitance
3.5
42
3.5
42
pF
pF
CPD
power dissipation capacitance per latch
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
PIN DESCRIPTION
PIN NO.
SYMBOL
1Q to 4Q
1D to 4D
LE3-4
NAME AND FUNCTION
1, 14, 11, 8
complementary latch outputs
data inputs
2, 3, 6, 7
4
latch enable input, latches 3 and 4 (active HIGH)
positive supply voltage
5
VCC
12
GND
ground (0 V)
13
LE1-2
latch enable input, latches 1 and 2 (active HIGH)
latch outputs
16, 15, 10, 9
1Q to 4Q
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
FUNCTION TABLE
INPUTS
LEn-n
OUTPUTS
nQ nQ
OPERATING
MODES
nD
H
H
L
H
L
H
H
L
data enabled
data latched
L
X
q
q
Notes
1. H = HIGH voltage level
L = LOW voltage level
q = lower case letters indicate the state of the
referenced output one set-up time prior
to the HIGH-to-LOW LEn-n transition
X = don’t care
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
+25
−40 to+85 −40 to+125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nD to nQ
33
12
10
110
22
19
140
28
24
165
33
28
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
t
t
t
t
PHL/ tPLH propagation delay
nD to nQ
39
14
11
120
24
20
150
30
26
180
36
31
2.0 Fig.7
4.5
6.0
PHL/ tPLH propagation delay
LEn-n to nQ
33
12
10
120
24
20
150
30
26
180
36
31
2.0 Fig.8
4.5
6.0
PHL/ tPLH propagation delay
LEn-n to nQ
39
14
11
125
25
21
155
31
26
190
38
32
2.0 Fig.8
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Figs 6 and 7
4.5
6.0
tW
tsu
th
enable pulse width
HIGH
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
set-up time
nD to LEn-n
60
12
10
14
5
4
75
15
13
90
18
15
2.0 Fig.9
4.5
6.0
hold time
3
3
3
−8
−3
−2
3
3
3
3
3
3
2.0 Fig.9
4.5
6.0
nD to LEn-n
December 1990
5
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
nD
LEn-n
0.75
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nD to nQ
15
15
13
15
7
28
28
28
30
15
35
35
35
38
19
42
42
42
45
22
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.7
4.5 Fig.8
4.5 Fig.8
4.5 Figs 6 and 7
4.5 Fig.8
4.5 Fig.9
4.5 Fig.9
t
t
t
t
PHL/ tPLH propagation delay
nD to nQ
PHL/ tPLH propagation delay
LEn-n to nQ
PHL/ tPLH propagation delay
LEn-n to nQ
THL/ tTLH output transition time
tW
tsu
th
enable pulse width
HIGH
16
12
3
4
20
15
3
24
18
3
set-up time
nD to LEn-n
4
hold time
−2
nD to LEn-n
December 1990
6
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the data input (nD) to
output (nQ) propagation delays and the
output transition times.
Fig.6 Waveforms showing the data input (nD) to
output (nQ) propagation delays and the
output transition times.
The shaded areas indicate when the input is permitted to change
for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the data set-up and
hold times for nD input to LEn-n input.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the latch enable input
(LEn-n) pulse width, the latch enable input to
outputs (nQ, nQ) propagation delays and
the output transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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