74HC7731PW-T [NXP]
IC HC/UH SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, Shift Register;
| 型号： | 74HC7731PW-T |
| 厂家： | 
NXP |
| 描述： | IC HC/UH SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, Shift Register 移位寄存器 |
| 文件： | 总8页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7731
Quad 64-bit static shift register
September 1993
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
FEATURES
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
• Frequency range DC to 100 MHz.
• Separate serial data inputs
• Cascadable
TYP.
SYMBOL
PHL/tPLH
fmax
PARAMETER
CONDITIONS
UNIT
ns
HC HCT
15 20
• Functionally compatible with
HEF 4731
t
propagation delay
CPa-d to Qa-d
CL = 15 pF;
VCC = 5 V
• Includes recycling mode
• Direct shift out
maximum clock
frequency
100 100
3.5 3.5
MHz
CI
input capacitance
power dissipation
capacitance per register and 3
pF
pF
• Output capability: Standard
• ICC category: LSI.
CPD
notes 1, 2
58
61
Notes
APPLICATIONS
1. CPD is used to determine the dynamic power dissipation (PD in µW):
• Data storage
• Delay line.
PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC
where:
)
fi = input frequency in MHz.
fo = output frequency in MHz.
GENERAL DESCRIPTION
V
CC = supply voltage in V.
The HC/HCT7731 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no. 7A.
CL = output load capacitance in pF.
Ipull-up = pull-up currents in µA.
2. For HC the condition is VI = GND to VCC
The HC/HCT7731 are quad 64-bit
static shift registers with a recycling
mode. Each register has separate
data inputs Da to Dd, clock inputs CPa
to CPd and data outputs Qa to Qd.
Data shifts one place towards the
output, each LOW to HIGH transition
of the clock pulse. Each recycling
mode input controls two registers
RECab for registers A and B and
RECcd for registers C and D. When
the REC input is HIGH, the device is
in the recycling mode and data at the
output is shifted back into the input of
the register, so after 64 clock pulses
the contents of a register is again in
its original position. This enables the
user to tap off data from any position.
When the REC input is LOW external
data can be shifted in.
For HCT the condition is VI = GND to VCC − 1.5 V.
3. See also power dissipation information.
ORDERING INFORMATION
PACKAGE
EXTENDED TYPE
NUMBER
PINS
16
PIN POSITION MATERIAL
CODE
SOT38Z
SOT109A
74HC/HCT7731N
74HC/HCT7731D
DIL
plastic
plastic
16
SO16
September 1993
2
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
PINNING
SYMBOL
Qa to Qd
PIN
DESCRIPTION
data outputs
1, 7, 9, 15
handbook, halfpage
V
16
CPa to CPd
Da to Dd
RECab, RECcd
GND
2, 6, 10, 14 clock inputs
3, 5, 11, 13 data inputs
Q
1
2
3
4
5
6
7
8
a
a
a
CC
CP
Q
d
15
14
13
4, 12
8
recycled enable input
CP
D
d
ground (0 V)
D
d
REC
ab
VCC
16
positive supply
7731
D
12 REC
cd
b
b
b
D
CP
11
10
9
c
CP
Q
c
Q
c
GND
MBA341
Fig.1 Pin configuration.
D
a
3
2
MUX
MUX
MUX
MUX
64 - BIT
STATIC SHIFT
REGISTER
Q
Q
a
b
1
7
CP
a
REC
ab
4
5
D
b
64 - BIT
STATIC SHIFT
REGISTER
CP
b
6
D
c
11
10
12
13
64 - BIT
STATIC SHIFT
REGISTER
Q
Q
c
9
CP
c
REC
cd
D
d
64 - BIT
STATIC SHIFT
REGISTER
15
d
CP
d
14
MBA342
Fig.2 Functional diagram.
September 1993
3
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
REC
n
Q
n
D
Q
D
Q
D
Q
FF1
CP
FF64
CP
FF2
CP
D
n
MBA345
CP
n
to second shift register
Fig.3 Logic diagram.
FUNCTION TABLE
INPUT
OUTPUT
REC
L
CP
↑
MODE
shift
H
↑
recycle
Notes
1. L = LOW voltage level
H = HIGH voltage Level
↑ = LOW-to-HIGH CP transition
September 1993
4
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: LSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
TEST CONDITION
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN TYP MAX MIN MAX MIN MAX
t
PHL/tPLH propagation
delay time CP
to Qn
−
−
−
50
18
15
155
31
26
−
−
−
190
38
32
−
−
−
230
46
39
ns
ns
ns
2.0
4.5
6.0
Fig.4
t
THL/tTLH
outputtransition
time
−
−
−
19
7
6
75
15
13
−
−
−
90
18
15
−
−
−
110
22
19
ns
ns
ns
2.0
4.5
6.0
Fig.4
tW
tsu
tsu
th
clock pulse
width
HIGH or LOW
80
16
14
19
7
6
−
−
−
100
20
17
−
−
−
120
24
20
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.4
set-up time Dn
to CPn
60
12
10
8
3
3
−
−
−
75
15
13
−
−
−
90
18
15
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.4
set-up time
RECn to CPn
75
15
13
22
8
7
−
−
−
90
18
15
−
−
−
110
22
19
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.5
hold time Dn to 25
CPn
−3
−1
−1
−
−
−
30
6
5
−
−
−
35
7
6
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.4
5
4
th
hold time RECn 10
−8
−3
−3
−
−
−
10
2
2
−
−
−
15
3
3
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.5
to CPn
2
2
fmax
maximum clock
pulse frequency 30
35
6
26
78
93
−
−
−
4.8
24
28
−
−
−
4
20
23
−
−
−
MHz 2.0
MHZ 4.5
MHz 6.0
Fig.4 (note 1)
Note
1. The maximum power dissipation has to be observed. See power dissipation information.
September 1993
5
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
UNIT LOAD COEFFICIENT
UNIT LOAD
INPUT
COEFFICIENT
CPn
RECn
Dn
0.7
0.4
0.5
Notes
1. The RS input has CMOS input switching levels.
2. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To
determine ∆ICC per input, multiply this value by the unit load coefficient shown in Table 1.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
−40 to +85 −40 to +125 UNIT
MIN TYP MAX MIN MAX MIN MAX
TEST CONDITION
SYMBOL
PARAMETER
+25
VCC
(V)
WAVEFORMS
Fig.4
tPHL/tPLH propagation delay time
CP to Qn
−
24
42
15
−
−
52
18
−
−
63
22
−
ns
ns
ns
ns
ns
ns
ns
4.5
t
THL/tTLH
output transmission time
−
7
−
−
4.5
4.5
4.5
2
Fig.4
tW
tsu
tsu
th
clock pulse width
HIGH or LOW
16
12
7
20
15
18
6
24
18
22
7
Fig.4
set-up time Dn to CPn
3
−
−
−
Fig.4
set-up time RECn to CPn 15
6
−
−
−
Fig.5
hold time Dn to CPn
5
0
−
−
−
2
Fig.4
th
hold time RECn to CPn
2
−3
80
−
2
−
3
−
4.5
Fig.5
fmax
maximum clock pulse
frequency
30
−
24
−
20
−
MHz 4.5
Fig.4 (note 1)
September 1993
6
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
AC WAVEFORMS
1/ f
max
(1)
CP INPUT
n
V
M
t
W
t
t
su
su
t
t
h
h
(1)
D
INPUT
V
n
M
t
t
PHL
PLH
(1)
V
Q
OUTPUT
M
n
t
t
THL
MBA320
TLH
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
Fig.4 Waveforms showing the clock (CP) and data (D) input to output (Q) propagation delay, set-up, hold and
transition times.
1/ f
max
(1)
CP INPUT
n
V
M
t
W
t
t
su
su
t
t
h
h
(1)
REC INPUT
n
V
M
MBA321
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
Fig.5 Waveforms showing the clock (CP) to recycle (REC) set-up and hold times.
September 1993
7
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
POWER DISSIPATION INFORMATION
The power dissipation per register operating at the same
frequency is given by:
PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC
)
MLA166
60
fi
= clock input frequency
handbook, halfpage
fo
= data output frequency
C
PD
(pF)
CL
VCC
= output load capacitance in pF
= power supply voltage in V.
40
As PD also depends on the frequency at which the
contents of the internal bits are changing, the value of CPD
is a function of the duty factor (df) being the ration between
data and clock frequency, see Fig.6.
20
Example:
fi
= 12 MHz
= 3 MHz
= 25 pF
0
fo
0.2
0.4
0
0.6
duty factor
CL
VCC
df
= 5 V
= 3/12 = 0.25
CPD
= 42.5 pF
PD = (42.5 × 52 × 12) + (25 × 52 × 3) = 14625 µW
Fig.6 CPD as a function of the duty factor.
As the maximum allowable power dissipation in an SO
package at Tamb = 125 °C is 60 mW, it is allowed to apply
4 registers at the same time under these conditions.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
8
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