74HCT109D,653 [NXP]
74HC(T)109 - Dual JK flip-flop with set and reset; positive-edge trigger SOP 16-Pin;
| 型号： | 74HCT109D,653 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)109 - Dual JK flip-flop with set and reset; positive-edge trigger SOP 16-Pin 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT109
Dual JK flip-flop with set and reset;
positive-edge trigger
1997 Nov 25
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
(SD) and reset (RD) inputs; also complementary Q and Q
outputs.
FEATURES
• J, K inputs for easy D-type flip-flop
• Toggle flip-flop or “do nothing” mode
• Output capability: standard
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
• ICC category: flip-flops
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The JK design allows operation as a D-type flip-flop by
tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
The 74HC/HCT109 are dual positive-edge triggered, JK
flip-flops with individual J, K inputs, clock (CP) inputs, set
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PHL/ tPLH
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
t
nCP to nQ, nQ
nSD to nQ, nQ
15
12
12
75
17
14
15
61
ns
CL = 15 pF;
CC = 5 V
ns
V
nRD to nQ, nQ
ns
fmax
CI
maximum clock frequency
input capacitance
MHz
pF
3.5
20
3.5
22
CPD
power dissipation
capacitance per flip-flop
pF
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V.
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
1997 Nov 25
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 15
2, 14, 3, 13
4, 12
5, 11
6, 10
7, 9
1RD, 2RD
1J, 2J, 1K, 2K
1CP, 2CP
1SD, 2SD
1Q, 2Q
asynchronous reset-direct input (active LOW)
synchronous inputs; flip-flops 1 and 2
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true flip-flop outputs
1Q, 2Q
complement flip-flop outputs
8
GND
ground (0 V)
16
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1997 Nov 25
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
FUNCTION TABLE
INPUTS
CP
OUTPUTS
OPERATING
MODE
SD
RD
J
K
Q
Q
asynchronous set
asynchronous reset
undetermined
toggle
L
H
L
H
L
X
X
X
↑
X
X
X
h
l
X
X
X
l
H
L
L
H
H
q
L
H
q
H
H
H
H
H
H
H
H
load “0” (reset)
load “1” (set)
↑
l
L
H
L
↑
h
l
h
h
H
q
hold “no change”
↑
q
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time
prior to the LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
Fig.4 Functional diagram.
Q
C
C
C
C
C
C
C
C
K
Q
J
S
R
C
C
CP
MBK217
Fig.5 Logic diagram (one flip-flop).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
1997 Nov 25
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
74HC
TEST CONDITIONS
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
50
18
14
175
35
30
220
44
37
265
53
45
2.0
4.5
6.0
propagation delay
nCP to nQ, nQ
tPHL/ tPLH
ns
Fig.6
Fig.7
Fig.7
Fig.7
Fig.7
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
Fig.6
Fig.6
30
11
9
120
24
20
150
30
26
180
36
31
2.0
4.5
6.0
propagation delay
nSD to nQ
tPLH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
41
15
12
155
31
26
195
39
33
235
47
40
2.0
4.5
6.0
propagation delay
nSD to nQ
tPHL
41
15
12
185
37
31
230
46
39
280
56
48
2.0
4.5
6.0
propagation delay
nRD to nQ
tPHL
39
14
11
170
34
29
215
43
37
255
51
43
2.0
4.5
6.0
propagation delay
nRD to nQ
tPLH
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
output transition
time
tTHL/ tTLH
80
16
14
19
7
6
100
20
17
120
24
20
2.0
4.5
6.0
clock pulse width
HIGH or LOW
tW
tW
trem
tsu
th
80
16
14
14
5
4
100
20
17
120
24
20
2.0
4.5
6.0
set or reset pulse
width HIGH or LOW
70
14
12
19
7
6
90
18
15
105
21
18
2.0
4.5
6.0
removal time
nSD, nRD to nCP
70
14
12
17
6
5
90
18
15
105
21
18
2.0
4.5
6.0
set-up time
nJ, nK to nCP
5
5
5
0
0
0
5
5
5
5
5
5
2.0
4.5
6.0
hold time
nJ, nK to nCP
6.0
30
35
22
68
81
5.0
24
28
4.0
20
24
2.0
4.5
6.0
maximum clock
pulse frequency
fmax
1997 Nov 25
5
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85
−40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
propagation delay
nCP to nQ, nQ
t
PHL/ tPLH
20
13
19
19
35
26
35
35
44
33
44
44
53
39
53
53
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
propagation delay
nSD to nQ
tPLH
propagation delay
nSD to nQ
tPHL
propagation delay
nRD to nQ
tPHL
propagation delay
nRD to nQ
tPLH
16
7
32
15
40
19
48
22
ns
ns
ns
4.5 Fig.7
4.5 Fig.6
4.5 Fig.6
tTHL/ tTLH output transition time
clock pulse width
HIGH or LOW
tW
18
16
16
18
3
9
23
20
20
23
3
27
24
24
27
3
set or reset pulse width
HIGH or LOW
tW
8
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.7
4.5 Fig.6
4.5 Fig.6
removal time
trem
8
nSD, nRD to nCP
set-up time
tsu
8
nJ, nK to nCP
hold time
nJ, nK to nCP
th
−3
55
maximum clock
fmax
27
22
18
MHz 4.5 Fig.6
pulse frequency
1997 Nov 25
6
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
AC WAVEFORMS
The shaded areas indicate when the
input is permitted to change for
predictable output performance.
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ,
nK to nCP set-up, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse
frequency.
(1)
V
M
nCP INPUT
t
rem
(1)
t
V
nS INPUT
D
M
t
W
rem
t
W
(1)
V
nR INPUT
D
M
t
t
PHL
PLH
(1)
nQ OUTPUT
nQ OUTPUT
V
M
t
t
PLH
PHL
(1)
V
M
MBK216
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set
and reset pulse widths and the nRD, nSD to nCP removal time.
1997 Nov 25
7
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
WAVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
DIP
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Even with these conditions:
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
SO, SSOP and TSSOP
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
REPAIRING SOLDERED JOINTS
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
1997 Nov 25
8
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Nov 25
9
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