74HCT161PW,118 [NXP]
74HC(T)161 - Presettable synchronous 4-bit binary counter; asynchronous reset TSSOP 16-Pin;
| 型号： | 74HCT161PW,118 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)161 - Presettable synchronous 4-bit binary counter; asynchronous reset TSSOP 16-Pin 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT161
Presettable synchronous 4-bit
binary counter; asynchronous reset
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive-edge triggered clock
• Asynchronous reset
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level regardless
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The 74HC/HCT161 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT161 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
1
The outputs (Q0 to Q3) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
--------------------------------------------------------------------------------------------------
fmax
=
tP(max) (CP to TC) + tSU (CEP to CP)
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
TYPICAL
SYMBOL PARAMETER
CONDITIONS
UNIT
1. CPD is used to determine the
dynamic power dissipation
(PD in µW):
HC HCT
t
PHL/ tPLH propagation delay
CP to Qn
CL = 15 pF;
VCC = 5 V
19
20
24
25
26
14
ns
ns
ns
ns
ns
PD = CPD × VCC2 × fi +
∑ (CL × VCC2 × fo)
where:
CP to TC
MR to Qn
MR to TC
CET to TC
21
20
20
10
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of
fmax
CI
maximum clock frequency
input capacitance
44
45
3.5
35
MHz
pF
3.5
outputs
CPD
power dissipation
notes 1 and 2 33
pF
CL = output load capacitance in
pF
capacitance per package
VCC = supply voltage in V
2. For HC the condition is
VI = GND to VCC
For HCT the condition is
VI = GND to VCC − 1.5 V
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
MR
asynchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data inputs
2
CP
3, 4, 5, 6
D0 to D3
CEP
GND
PE
7
count enable input
8
ground (0 V)
9
parallel enable input (active LOW)
count enable carry input
flip-flop outputs
10
CET
Q0 to Q3
TC
14, 13, 12, 11
15
16
terminal count output
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
INPUTS
CEP CET
OUTPUTS
MR
CP
PE
Dn
Qn
TC
reset (clear)
parallel load
L
X
X
X
X
X
L
L
H
H
↑
↑
X
X
X
X
I
I
I
h
L
H
L
(1)
(1)
(1)
L
count
H
↑
h
h
h
X
count
hold
(do nothing)
H
H
X
X
I
X
X
I
h
h
X
X
qn
qn
Note
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
December 1990
4
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
Fig.5 State diagram.
Fig.6 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen,
zero, one and two; inhibit.
December 1990
5
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
Fig.7 Logic diagram.
December 1990
6
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85
−40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
61
22
18
190
38
32
240
48
41
285
57
48
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
Fig.8
t
PHL/ tPLH propagation delay
CP to TC
69
25
20
215
43
37
270
54
46
325
65
55
2.0
4.5
6.0
Fig.8
tPHL
propagation delay
MR to Qn
63
23
18
210
42
36
265
53
45
315
63
54
2.0
4.5
6.0
Fig.9
tPHL
propagation delay
MR to TC
63
23
18
220
44
37
275
55
47
330
66
56
2.0
4.5
6.0
Fig.9
t
PHL/ tPLH propagation delay
CET to TC
33
12
10
150
30
26
190
38
33
225
45
38
2.0
4.5
6.0
Fig.10
Figs 8 and 10
Fig.8
tTHL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
2.0
4.5
6.0
tW
master reset pulse
width; LOW
80
16
14
19
7
6
100
20
17
120
24
20
2.0
4.5
6.0
Fig.9
trem
tsu
tsu
removal time
MR to CP
100 19
125
25
21
150
30
26
2.0
4.5
6.0
Fig.9
20
17
7
6
set-up time
Dn to CP
80
16
14
25
9
7
100
20
17
120
24
20
2.0
4.5
6.0
Fig.11
Fig.11
set-up time
PE to CP
100 30
125
25
21
150
30
26
2.0
4.5
6.0
20
17
11
9
December 1990
7
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
T
amb (°C)
74HC
TEST CONDITIONS
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85
−40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tsu
set-up time
CEP, CET to CP
170 47
215
43
37
255
51
43
ns
2.0
4.5
6.0
Fig.12
34
29
17
14
th
hold time
Dn, PE, CEP,
CET to CP
0
0
0
−14
−5
−4
0
0
0
0
0
0
ns
2.0
4.5
6.0
Figs 11 and 12
Fig.8
fmax
maximum clock pulse 4.6
frequency
13
40
48
3.6
18
21
3.0
15
18
MHz
2.0
4.5
6.0
23
27
December 1990
8
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
MR
CP
0.95
1.10
0.25
0.25
0.75
0.30
CEP
Dn
CET
PE
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
74HCT
TEST CONDITIONS
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
23
28
29
30
17
7
43
48
46
51
35
15
54
60
58
64
44
19
65
72
69
77
53
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Fig.8
t
PHL/ tPLH propagation delay
CP to TC
Fig.8
tPHL
propagation delay
MR to Qn
Fig.9
tPHL
propagation delay
MR to TC
Fig.9
tPHL/ tPLH propagation delay
CET to TC
Fig.10
Figs 8 and 10
Fig.8
t
THL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
16
20
20
7
20
25
25
24
30
30
tW
master reset pulse
width; LOW
10
6
Fig.9
trem
removal time
MR to CP
Fig.9
December 1990
9
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
T
amb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
tsu
tsu
tsu
th
set-up time
Dn to CP
18
30
40
0
8
23
38
50
0
27
45
60
0
ns
ns
ns
ns
4.5
4.5
4.5
4.5
Fig.11
set-up time
PE to CP
17
17
−7
Fig.11
set-up time
CEP, CET to CP
Fig.12
hold time
Figs 11 and 12
Dn, PE, CEP,
CET to CP
fmax
maximum clock pulse 23
frequency
41
18
15
MHz 4.5
Fig.8
December 1990
10
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn, TC) propagation
delays and the master reset to clock (CP) removal time.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times.
December 1990
11
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
The shaded areas indicate when the input is permitted to change
for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input PE.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
12
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