74HCT163DB [NXP]
Presettable synchronous 4-bit binary counter; synchronous reset; 可预置同步4位二进制计数器;同步复位
| 型号： | 74HCT163DB |
| 厂家： | 
NXP |
| 描述： | Presettable synchronous 4-bit binary counter; synchronous reset |
| 文件： | 总11页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT163
Presettable synchronous 4-bit
binary counter; synchronous reset
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive-edge triggered clock
• Synchronous reset
For the “163” the clear function is synchronous.
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level after the
next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for
MR are met). This action occurs regardless of the levels at
PE, CET and CEP inputs.
• Output capability: standard
• ICC category: MSI
This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND
gate.
GENERAL DESCRIPTION
The 74HC/HCT163 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The 74HC/HCT163 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q0 to Q3) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
1
=
------------------------------------------------------------------------------------------------
fmax
tP (max) (CP to TC) + tSU(CEP to CP)
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
TYPICAL
HC HCT
SYMBOL
PARAMETER
CONDITIONS
UNIT
1. CPD is used to determine the
dynamic power dissipation
(PD in µW):
t
PHL/ tPLH propagation delay
CP to Qn
CL = 15 pF;
VCC = 5 V
PD = CPD × VCC2 × fi +
∑ (CL × VCC2 × fo)
17 20
21 25
11 14
ns
ns
ns
CP to TC
CET to TC
where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of
outputs
CL = output load capacitance in
pF
fmax
CI
maximum clock frequency
input capacitance
51 50
3.5 3.5
MHz
pF
CPD
power dissipation
capacitance per package
notes 1 and 2 33 35
pF
VCC = supply voltage in V
2. For HC the condition is
VI = GND to VCC
For HCT the condition is
VI = GND to VCC − 1.5 V
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
MR
synchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data inputs
2
CP
3, 4, 5, 6
D0 to D3
CEP
GND
PE
7
count enable input
8
ground (0 V)
9
parallel enable input (active LOW)
count enable carry input
flip-flop outputs
10
CET
Q0 to Q3
TC
14, 13, 12, 11
15
16
terminal count output
VCC
positive supply voltage
Fig.2 Logic symbol.
Fig.1 Pin configuration.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
INPUTS
CEP CET
OUTPUTS
MR
CP
PE
Dn
Qn
TC
reset (clear)
parallel load
I
↑
X
X
X
X
L
L
h
h
↑
↑
X
X
X
X
I
I
I
h
L
H
L
(1)
(1)
(1)
L
count
h
↑
h
h
h
X
count
hold
(do nothing)
h
h
X
X
I
X
X
I
h
h
X
X
qn
qn
Notes
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
December 1990
4
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
Fig.5 State diagram.
Fig.6 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen,
zero, one and two; inhibit.
December 1990
5
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
Fig.7 Logic diagram.
December 1990
6
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
WAVEFORMS
74HC
SYMBOL
PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
55
20
16
185
37
31
230
46
39
280
56
48
2.0 Fig.8
4.5
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
PHL/ tPLH propagation delay
69
25
20
215
43
37
270
54
46
320
65
55
2.0 Fig.8
4.5
6.0
CP to TC
PHL/ tPLH propagation delay
CET to TC
36
13
10
120
24
20
150
30
26
180
36
31
2.0 Fig.9
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Figs 8 and 9
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
tsu
tsu
tsu
th
set-up time
MR, Dn to CP
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Figs 10 and 11
4.5
6.0
set-up time
PE to CP
80
16
14
22
8
6
100
20
17
120
24
20
2.0 Fig.10
4.5
6.0
set-up time
CEP, CET to CP
175 58
220
44
37
265
53
45
2.0 Fig.12
4.5
6.0
35
30
21
17
hold time
0
0
0
−14
−5
−4
0
0
0
0
0
0
2.0 Figs 10, 11 and 12
4.5
6.0
Dn, PE, CEP,
CET, MR to CP
fmax
maximum clock pulse
frequency
5
27
32
15
46
55
4
22
26
4
18
21
2.0 Fig.8
MHz 4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
MR
CP
0.95
1.10
0.25
0.25
0.75
0.30
CEP
Dn
CET
PE
December 1990
8
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
WAVEFORMS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
23
29
17
7
39
49
32
15
49
61
44
19
59
74
48
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.8
t
PHL/ tPLH propagation delay
CP to TC
4.5 Fig.8
t
PHL/ tPLH propagation delay
CET to TC
4.5 Fig.9
tTHL/ tTLH output transition time
4.5 Figs 8 and 9
4.5 Fig.8
tW
tsu
tsu
tsu
th
clock pulse width
HIGH or LOW
20
20
20
40
0
6
25
25
25
50
0
30
30
30
60
0
set-up time
MR, Dn to CP
9
4.5 Figs 10 and 11
4.5 Fig.10
set-up time
PE to CP
11
24
−5
set-up time
CEP, CET to CP
4.5 Fig.12
hold time
4.5 Figs 10, 11 and 12
Dn, PE, CEP,
CET, MR to CP
fmax
maximum clock pulse 26
frequency
45
21
17
MHz 4.5 Fig.8
December 1990
9
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE).
December 1990
10
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the MR set-up and hold times.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
APPLICATION INFORMATION
The HC/HCT163 facilitate designing counters of any
modulus with minimal external logic.
The output is glitch-free due to the synchronous reset.
Fig.14 Modulo-11 counter.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
Fig.13 Modulo-5 counter.
December 1990
11
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