74HCT174DB-T [NXP]
暂无描述;
NXP 
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT174
Hex D-type flip-flop with reset;
positive-edge trigger
1998 Jul 08
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
The 74HC/HCT174 have six edge-triggered D-type
FEATURES
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
• Six edge-triggered D-type flip-flops
• Asynchronous master reset
• Output capability: standard
• ICC category: MSI
The register is fully edge-triggered. The state of each D
input, one set-up time prior to the LOW-to-HIGH clock
transition, is transferred to the corresponding output of the
flip-flop.
GENERAL DESCRIPTION
A LOW level on the MR input forces all outputs LOW,
independently of clock or data inputs.
The 74HC/HCT174 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The device is useful for applications requiring true outputs
only and clock and master reset inputs that are common to
all storage elements.
QUICK REFERENCE DATA
GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PHL/ tPLH
PARAMETER
CONDITIONS
UNIT
HC
HCT
t
propagation delay
CP to Qn
CL = 15 pF; VCC = 5 V
17
13
99
3.5
18
17
69
3.5
ns
MR to Qn
ns
fmax
CI
maximum clock frequency
input capacitance
MHz
pF
power dissipation
capacitance per flip-flop
CPD
notes 1 and 2
17
17
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi +∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
1998 Jul 08
2
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
74HC174N;
74HCT174N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HC174D;
74HCT174D
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC174DB;
74HCT174DB
SSOP16
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
SOT403-1
74HC174PW;
74HCT174PW
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION
PIN NO.
SYMBOL
MR
NAME AND FUNCTION
asynchronous master reset (active LOW)
flip-flop outputs
1
2, 5, 7, 10, 12, 15
Q0 to Q5
D0 to D5
GND
3, 4, 6, 11, 13, 14
data inputs
8
ground (0 V)
9
CP
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
16
VCC
Fig.1 Pin configuration.
Fig.2
Fig.3 IEC logic symbol.
1998 Jul 08
3
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
CP
OUTPUTS
Qn
OPERATING MODES
MR
Dn
reset (clear)
load “1”
L
H
H
X
↑
X
h
I
L
H
L
load “0”
↑
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑= LOW-to-HIGH CP transition
Fig.5 Logic diagram.
1998 Jul 08
4
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
Fig.6
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
55
20
16
44
16
13
19
7
165
33
205
41
250
50
ns
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
28
35
43
tPHL
propagation delay
MR to Qn
150
30
190
38
225
45
Fig.7
26
33
38
tTHL/ tTLH output transition time
75
95
110
22
Fig.6
15
19
6
13
16
19
tW
tW
trem
tsu
th
clock pulse width
HIGH or LOW
80
16
14
80
16
14
5
17
6
100
20
17
100
20
17
5
120
24
20
120
24
20
5
Fig.6
5
master reset pulse
width; LOW
12
4
Fig.7
3
removal time
MR to CP
−11
−4
−3
6
Fig.7
5
5
5
5
5
5
set-up time
Dn to CP
60
12
10
3
75
15
13
3
90
18
15
3
Fig.8
2
2
hold time
Dn to CP
−6
−2
−2
30
90
107
Fig.8
3
3
3
3
3
3
fmax
maximum clock pulse
frequency
6
5
4
MHz 2.0
4.5
Fig.6
30
35
24
28
20
24
6.0
1998 Jul 08
5
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Dn
0.25
1.30
1.25
CP
MR
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL/ tPLH propagation delay
21
20
7
35
35
15
44
44
19
53
53
22
ns
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Fig.6
Fig.7
Fig.6
Fig.6
Fig.7
Fig.7
Fig.8
Fig.8
Fig.6
CP to Qn
tPHL
propagation delay
MR to Qn
ns
tTHL/ tTLH output transition time
ns
tW
tW
trem
tsu
th
clock pulse width
HIGH or LOW
16
20
7
20
25
15
20
5
24
30
18
24
5
ns
master reset pulse
width; LOW
7
ns
removal time MR to CP 12
−3
4
ns
set-up time Dn to CP
hold time Dn to CP
16
5
ns
−3
63
ns
fmax
maximum clock pulse
frequency
30
24
20
MHz
1998 Jul 08
6
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the master reset (MR)
pulse width, the master reset to output (Qn)
propagation delays and the master reset to
clock (CP) removal time.
Fig.6 Waveforms showing the clock (CP) to output
(Qn) propagation delays, the clock pulse
width, the output transition times and the
maximum clock pulses frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to
change for predictable output performance
Fig.8 Waveforms showing the data set-up and hold times for the data input (Dn).
1998 Jul 08
7
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
max.
min.
max.
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
3.9
3.4
8.25
7.80
9.5
8.3
4.7
0.51
3.7
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.021
0.015
0.013
0.009
0.86
0.84
0.32
0.31
0.055
0.045
0.26
0.24
0.15
0.13
0.37
0.33
inches
0.19
0.020
0.15
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-10-02
95-01-19
SOT38-1
050G09
MO-001AE
1998 Jul 08
8
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1998 Jul 08
9
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2.0
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-01-14
95-02-04
SOT338-1
MO-150AC
1998 Jul 08
10
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-07-12
95-04-04
SOT403-1
MO-153
1998 Jul 08
11
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
Several techniques exist for reflowing; for example,
SOLDERING
Introduction
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
DIP
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Even with these conditions:
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
REPAIRING SOLDERED JOINTS
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
SO, SSOP and TSSOP
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1998 Jul 08
12
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less
than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a
dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jul 08
13
相关型号：
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NXP
74HCT174PW-Q100J
74HC(T)174-Q100 - Hex D-type flip-flop with reset; positive-edge trigger TSSOP 16-Pin
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