74HCT174PW-Q100 [NXP]
HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16;型号: | 74HCT174PW-Q100 |
厂家: | NXP |
描述: | HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16 光电二极管 输出元件 逻辑集成电路 触发器 |
文件: | 总16页 (文件大小:152K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC174-Q100; 74HCT174-Q100
Hex D-type flip-flop with reset; positive-edge trigger
Rev. 1 — 17 April 2013
Product data sheet
1. General description
The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops
with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master
reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the
set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the
flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to
be reset LOW. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC174-Q100: CMOS level
For 74HCT174-Q100: TTL level
Six edge-triggered D-type flip-flops
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC174D-Q100
74HCT174D-Q100
74HC174PW-Q100
74HCT174PW-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads; body width SOT109-1
3.9 mm
40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
4. Functional diagram
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Fig 1. Logic symbol
Fig 2. IEC logic symbol
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Fig 3. Logic diagram
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
2 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
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Fig 4. Pin configuration SO16
Fig 5. Pin configuration TSSOP16
5.2 Pin description
Table 2.
Symbol
MR
Pin description
Pin
Description
1
asynchronous master reset input (active LOW)
flip-flop output
Q0 to Q5
D0 to D5
GND
2, 5, 7, 10, 12, 15
3, 4, 6, 11, 13, 14
data input
8
ground (0 V)
CP
9
clock input (LOW-to-HIGH edge-triggered)
positive supply voltage
VCC
16
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
3 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
6. Functional description
Table 3.
Function table[1]
Operating modes
Inputs
Outputs
MR
L
CP
X
Dn
X
h
Qn
L
reset (clear)
load “1”
H
H
load “0”
H
l
L
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
20
20
25
50
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
4 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC174-Q100
74HCT174-Q100
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
-
40
-
C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Max
74HC174-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VI = VIH or VIL
1.5
1.2
-
1.5
-
-
-
1.5
-
-
-
V
V
V
V
V
V
3.15 2.4
-
3.15
3.15
4.2
3.2
0.8
2.1
2.8
-
4.2
4.2
VIL
LOW-level
input voltage
-
-
-
0.5
1.35
1.8
-
-
-
0.5
-
-
-
0.5
1.35
1.8
1.35
1.8
VOH
HIGH-level
output voltage
IO = 20 A; VCC = 2.0 V 1.9
IO = 20 A; VCC = 4.5 V 4.4
IO = 20 A; VCC = 6.0 V 5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
4.4
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
V
0.1
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
5 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Max
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
74HCT174-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
IO = 5.2 mA; VCC = 5.5 V
-
-
-
0
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
1
V
0.15 0.26
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160
A
additional
supply current VI = VCC 2.1 V;
other inputs at VCC or GND;
per input pin;
VCC = 4.5 V to 5.5 V
Dn input
-
-
-
-
25
90
-
-
-
-
112.5
585
562.5
-
-
-
-
-
122.5
637
612.5
-
A
A
A
pF
CP input
130 468
125 450
MR input
CI
input
3.5
-
capacitance
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
74HC174-Q100
[1]
tpd
propagation
delay
CP to Qn; see Figure 6
VCC = 2.0 V
-
-
-
-
55
20
17
16
165
33
-
-
-
-
-
205
-
-
-
-
250
ns
ns
ns
ns
VCC = 4.5 V
41
-
50
-
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
28
35
43
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
6 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
tPHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 7
VCC = 2.0 V
-
-
-
-
44
16
13
13
150
30
-
-
-
-
-
190
-
-
-
-
225
ns
ns
ns
ns
VCC = 4.5 V
38
-
45
-
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
26
33
38
[2]
tt
transition time
pulse width
Qn output; see Figure 6
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
CP input HIGH or LOW;
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
5
17
20
MR input LOW;
see Figure 7
VCC = 2.0 V
80
16
14
12
4
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
V
CC = 4.5 V
VCC = 6.0 V
MR to CP; see Figure 7
VCC = 2.0 V
3
17
20
trec
recovery time
set-up time
hold time
+5
+5
+5
11
4
-
-
-
+5
+5
+5
-
-
-
+5
+5
+5
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
tsu
Dn to CP; see Figure 6
VCC = 2.0 V
60
12
10
6
2
2
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
th
Dn to CP; see Figure 6
VCC = 2.0 V
+3
+3
+3
6
2
2
-
-
-
+3
+3
+3
-
-
-
+3
+3
+3
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum
frequency
CP input; see Figure 6
VCC = 2.0 V
6
30
90
107
99
-
-
-
-
-
5
-
-
-
-
-
4
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
30
35
-
24
28
-
20
24
-
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
[3]
CPD
power
per package;
-
17
-
-
dissipation
capacitance
VI = GND to VCC
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
7 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
74HCT174-Q100
[1]
tpd
propagation
delay
CP to Qn; see Figure 6
VCC = 4.5 V
-
-
21
18
35
-
-
-
44
-
-
53
ns
ns
VCC = 5.0 V; CL = 15 pF
MR to Qn; see Figure 7
VCC = 4.5 V
-
-
tPHL
HIGH to LOW
propagation
delay
-
-
20
17
35
-
-
-
44
-
-
-
53
-
ns
ns
VCC = 5.0 V; CL = 15 pF
Qn output; see Figure 6
VCC = 4.5 V
[2]
tt
transition time
pulse width
-
7
7
15
-
-
19
-
-
22
-
ns
ns
tW
CP input; see Figure 6
VCC = 4.5 V
16
20
24
MR input LOW;
see Figure 7
VCC = 4.5 V
20
12
16
5
7
-
-
-
-
25
15
20
5
-
-
-
-
30
18
24
5
-
-
-
-
ns
ns
ns
ns
trec
recovery time
set-up time
hold time
MR to CP; see Figure 7
VCC = 4.5 V
3
4
tsu
Dn to CP; see Figure 6
VCC = 4.5 V
th
Dn to CP; see Figure 6
VCC = 4.5 V
3
fmax
maximum
frequency
CP input; see Figure 6
VCC = 4.5 V
30
-
63
69
17
-
-
-
24
-
-
-
-
20
-
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
[3]
CPD
power
per package;
-
-
-
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
8 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
11. Waveforms
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ꢔ
ꢖꢗ
ꢖꢗ
ꢂꢜꢝ
!"
ꢐ
#
ꢉꢊ&'%(ꢗꢔ
ꢐ
ꢇ
ꢑꢒꢀ
ꢔ
ꢛ
ꢔ
ꢔ
ꢊꢘꢙ
ꢊꢙꢘ
ꢐ
$ꢘ
ꢋꢁ&*
ꢋꢁ&*
ꢍ%&)ꢗꢔ(ꢗꢔ
ꢐ
ꢐ
ꢇ
ꢇ
ꢂꢁ&*
ꢂꢁ&*
ꢐ
$ꢙ
ꢔ
ꢔ
ꢚꢘꢙ
ꢚꢙꢘ
ꢀꢀꢀꢁꢂꢂꢃꢄꢇꢇ
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 6. Input to output propagation delay, output transition time, clock input pulse width, set-up and hold times
for data input and maximum frequency
ꢐ
#
ꢐ
ꢉꢊ&'%(ꢗꢔ
ꢇꢈ&'%(ꢗꢔ
ꢇ
ꢑꢒꢀ
ꢔ
+,-
ꢔ
ꢛ
ꢐ
#
ꢐ
ꢐ
ꢇ
ꢇ
ꢑꢒꢀ
ꢔ
ꢊꢘꢙ
ꢐ
$ꢘ
ꢍ%&)ꢗꢔ(ꢗꢔ
ꢐ
ꢇ
ꢐ
$ꢙ
ꢀꢀꢀꢁꢂꢂꢃꢄꢇꢉ
Measurement points are given in Table 8.
V
OL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Master reset to output propagation delays, master reset pulse width and master reset to clock recovery
time
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
9 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
Table 8.
Type
Measurement points
Input
Output
VI
VM
VM
74HC174-Q100
74HCT174-Q100
VCC
3 V
0.5VCC
1.3 V
0.5VCC
1.3 V
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 8. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC174-Q100
74HCT174-Q100
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
open
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
10 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 9. Package outline SOT109-1 (SO16)
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
11 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 10. Package outline SOT403-1 (TSSOP16)
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
12 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
ESD
HBM
MIL
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT174_Q100 v.1 20130417
Product data sheet
-
-
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
13 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
14 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT174_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
15 of 16
74HC174-Q100; 74HCT174-Q100
NXP Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 April 2013
Document identifier: 74HC_HCT174_Q100
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