74HCT190N [NXP]
Presettable synchronous BCD decade up/down counter; 可预置同步BCD十年向上/向下计数器
| 型号： | 74HCT190N |
| 厂家： | 
NXP |
| 描述： | Presettable synchronous BCD decade up/down counter |
| 文件： | 总13页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT190
Presettable synchronous BCD
decade up/down counter
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
Overflow/underflow indications are provided by two types
of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a
circuit reaches zero in the count-down mode or reaches “9”
in the count-up-mode. The TC output will remain HIGH
until a state change occurs, either by counting or
presetting, or until U/D is changed. Do not use the TC
output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the RC
output. When TC is HIGH and CE is LOW, the RC output
follows the clock pulse (CP). This feature simplifies the
design of multistage counters as shown in Figs 5 and 6.
FEATURES
• Synchronous reversible counting
• Asynchronous parallel load
• Count enable control for synchronous expansion
• Single up/down control input
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT190 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
In Fig.5, each RC output is used as the clock input to the
next higher stage. It is only necessary to inhibit the first
stage to prevent counting in all stages, since a HIGH on
CE inhibits the RC output pulse as indicated in the function
table. The timing skew between state changes in the first
and last stages is represented by the cumulative delay of
the clock as it ripples through the preceding stages. This
can be a disadvantage of this configuration in some
applications.
The 74HC/HCT190 are asynchronously presettable
up/down BCD decade counters. They contain four
master/slave flip-flops with internal gating and steering
logic to provide asynchronous preset and synchronous
count-up and count-down operation.
Fig.6 shows a method of causing state changes to occur
simultaneously in all stages. The RC outputs propagate
the carry/borrow signals in ripple fashion and all clock
inputs are driven in parallel. In this configuration the
duration of the clock LOW state must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes
HIGH. Since the RC output of any package goes HIGH
shortly after its CP input goes HIGH there is no such
restriction on the HIGH-state duration of the clock.
Asynchronous parallel load capability permits the counter
to be preset to any desired number. Information present on
the parallel data inputs (D0 to D3) is loaded into the counter
and appears on the outputs when the parallel load (PL)
input is LOW. As indicated in the function table, this
operation overrides the counting function.
Counting is inhibited by a HIGH level on the count enable
(CE) input. When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The up/down (U/D) input signal determines
the direction of counting as indicated in the function table.
The CE input may go LOW when the clock is in either
state, however, the LOW-to-HIGH CE transition must
occur only when the clock is HIGH. Also, the U/D input
should be changed only when either CE or CP is HIGH.
In Fig.7, the configuration shown avoids ripple delays and
their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a
given stage. An enable must be included in each carry
gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the
simple inhibit scheme of Figs 5 and 6 does not apply.
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
QUICK REFERENCE DATA
GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns
TYPICAL
UNIT
SYMBOL
PARAMETER
CONDITIONS
HC
HCT
t
PHL/ tPLH
propagation delay CP to Qn
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V
22
28
3.5
36
24
ns
fmax
CI
30
3.5
38
MHz
pF
CPD
power dissipation capacitance per flip-flop notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
3
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
PIN DESCRIPTION
PIN NO.
SYMBOL
Q0 to Q3
CE
NAME AND FUNCTION
3, 2, 6, 7
flip-flop outputs
4
count enable input (active LOW)
up/down input
5
U/D
8
GND
PL
ground (0 V)
11
parallel load input (active LOW)
terminal count output
12
TC
13
RC
ripple clock output (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data inputs
14
CP
15, 1, 10, 9
16
D0 to D3
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
4
December 1990
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
INPUTS
CE
OUTPUTS
PL
U/D
CP
Dn
Qn
L
L
X
X
X
X
X
X
L
H
L
H
parallel load
count up
H
H
H
L
H
X
I
I
↑
↑
X
X
X
count up
count down
hold (do nothing)
count down
no change
H
X
TC AND RC FUNCTION TABLE
INPUTS
TERMINAL COUNT STATE
OUTPUTS
U/D
CE
CP
Q0
Q1
Q2
Q3
TC
RC
H
L
L
H
H
L
X
X
H
H
H
X
X
X
X
X
X
H
H
H
L
H
H
H
L
H
H
H
H
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
Notes
1. H = HIGH voltage level
L
I
= LOW voltage level
= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑
= LOW-to-HIGH CP transition
= one LOW level pulse
= TC goes LOW on a LOW-to-HIGH CP transition
December 1990
5
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
Fig.5 N-stage ripple counter using ripple clock.
Fig.6 Synchronous n-stage counter using ripple carry/borrow.
Fig.7 Synchronous n-stage counter with parallel gated carry/borrow.
6
December 1990
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
Sequence
Load (present) to BCD seven;
count up to eight, nine, zero,
one and two;
inhibit;
count down to one, zero, nine,
eight and seven.
Fig.8 Typical load, count and inhibit sequence.
Fig.9 Logic diagram.
7
December 1990
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 TO +85 −40 TO +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
72
26
21
220
44
37
275
55
47
330
66
56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
Fig.10
Fig.10
Fig.11
Fig.11
Fig.12
Fig.13
Fig.14
Fig.14
Fig.15
Fig.10
Fig.15
t
t
t
t
PHL/ tPLH propagation delay
CP to TC
83
30
24
255
51
43
320
64
54
385
77
65
2.0
4.5
6.0
PHL/ tPLH propagation delay
CP to RC
44
16
13
150
30
26
190
38
33
225
45
38
2.0
4.5
6.0
PHL/ tPLH propagation delay
CE to RC
33
12
10
130
26
22
165
33
28
195
39
33
2.0
4.5
6.0
PHL/ tPLH propagation delay
Dn to Qn
63
23
18
220
44
37
275
55
47
330
66
56
2.0
4.5
6.0
tPHL/ tPLH propagation delay
PL to Qn
63
23
18
220
44
37
275
55
47
330
66
56
2.0
4.5
6.0
t
t
t
PHL/ tPLH propagation delay
U/D to TC
44
16
13
190
38
32
240
48
41
285
57
48
2.0
4.5
6.0
PHL/ tPLH propagation delay
U/D to RC
50
18
14
210
42
36
265
53
45
315
63
54
2.0
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
tW
clock pulse width
HIGH or LOW
155 28
195
39
33
235
47
40
2.0
4.5
6.0
31
26
10
8
tW
parallel load pulse width 100 25
125
25
21
150
30
26
2.0
4.5
6.0
LOW
20
17
9
7
December 1990
8
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 TO +85 −40 TO +125
min. typ. max. min. max. min. max.
trem
tsu
tsu
tsu
th
removal time
PL to CP
35
7
6
8
3
2
45
9
8
55
11
9
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
Fig.15
Fig.17
Fig.16
Fig.17
Fig.17
Fig.16
Fig.17
Fig.10
set-up time
U/D to CP
205 61
41
35
255
51
43
310
62
53
2.0
4.5
6.0
22
18
set-up time
Dn to PL
100 19
20
17
125
25
21
150
30
26
2.0
4.5
6.0
7
6
set-up time
CE to CP
140 39
28
24
175
35
30
210
42
36
2.0
4.5
6.0
14
11
hold time
U/D to CP
0
0
0
−44
−16
−13
0
0
0
0
0
0
2.0
4.5
6.0
th
hold time
Dn to PL
0
0
0
−14
−5
−4
0
0
0
0
0
0
2.0
4.5
6.0
th
hold time
CE to CP
0
0
0
−19
−7
−6
0
0
0
0
0
0
2.0
4.5
6.0
fmax
maximum clock pulse
frequency
3.0
15
18
8.3
25
30
2.4
12
14
2.0
10
12
MHz 2.0
4.5
6.0
December 1990
9
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Dn
0.5
CP
U/D
CE, PL
0.65
1.15
1.5
December 1990
10
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
28
34
20
18
24
29
24
26
7
48
58
35
33
44
49
45
45
15
60
73
44
41
55
61
56
56
19
72
87
53
50
66
74
68
68
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Fig.10
Fig.10
Fig.11
Fig.11
Fig.12
Fig.13
Fig.14
Fig.14
Fig.15
Fig.10
Fig.15
Fig.15
Fig.17
Fig.16
Fig.17
Fig.17
Fig.16
Fig.17
Fig.10
t
PHL/ tPLH propagation delay
CP to TC
t
PHL/ tPLH propagation delay
CP to RC
tPHL/ tPLH propagation delay
CE to RC
t
t
t
t
t
PHL/ tPLH propagation delay
Dn to Qn
PHL/ tPLH propagation delay
PL to Qn
PHL/ tPLH propagation delay
U/D to TC
PHL/ tPLH propagation delay
U/D to RC
THL/ tTLH output transition time
tW
tW
trem
tsu
tsu
tsu
th
clock pulse width
HIGH or LOW
25
10
12
1
31
28
9
38
33
11
63
30
47
0
parallel load pulse width 22
LOW
removal time
PL to CP
7
set-up time
U/D to CP
42
20
31
0
25
10
18
−18
−6
−10
27
53
25
39
0
set-up time
Dn to PL
set-up time
CE to CP
hold time
U/D to CP
th
hold time
Dn to PL
0
0
0
th
hold time
CE to CP
0
0
0
fmax
maximum clock pulse
frequency
16
13
11
MHz 4.5
December 1990
11
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width and the maximum clock pulse
frequency.
Fig.11 Waveforms showing the clock and count
enable inputs (CP, CE) to ripple clock
output (RC) propagation delays.
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the input (Dn) to output
(Qn) propagation delays.
Fig.13 Waveforms showing the input (PL) to output
(Qn) propagation delays.
(1) HC
:
VM = 50%;
VI = GND to
VCC
.
HCT :
VM = 1.3 V;
VI = GND to
3 V.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing the up/down count
input (U/D) to terminal count and ripple
clock output (TC, RC) propagation delays.
Fig.15 Waveforms showing the parallel load input
(PL) pulse width, removal time to clock (CP)
and the output (Qn) transition times.
December 1990
12
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (Dn).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the
clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
13
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