74HCT273D-Q100_技术文档

74HC273-Q100; 74HCT273-Q100

Octal D-type flip-flop with reset; positive-edge trigger

Rev. 1 — 19 June 2013

Product data sheet

1. General description

The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop.

The device features clock (CP) and master reset (MR) inputs. The outputs Qn assume the

state of their corresponding Dn inputs that meet the set-up and hold time requirements on

the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW

independently of clock and data inputs. Inputs include clamp diodes which enable the use

of current limiting resistors to interface inputs to voltages in excess of V_CC

.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Input levels:

 For 74HC273-Q100: CMOS level

 For 74HCT273-Q100: TTL level

 Common clock and master reset

 Eight positive edge-triggered D-type flip-flops

 Complies with JEDEC standard no. 7A

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V.

 Multiple package options

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC273D-Q100

74HCT273D-Q100

40 C to +125 C

SO20

plastic small outline package; 20 leads; body width SOT163-1

7.5 mm

74HC273PW-Q100 40 C to +125 C

TSSOP20

plastic thin shrink small outline package; 20 leads;

body width 4.4 mm

SOT360-1

74HCT273PW-Q100

74HC273BQ-Q100

74HCT273BQ-Q100

40 C to +125 C

DHVQFN20 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 20 terminals;

body 2.5  4.5  0.85 mm

SOT764-1

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

4. Functional diagram

11

CP

C1

1

R

MR

11

CP

3

2

1D

D0

Q0

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

3

4

2

3

4

2

5

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

4

7

8

5

6

9

5

D1

D2

D3

D4

D5

D6

D7

Q1

Q2

Q3

Q4

Q5

Q6

Q7

7

6

7

6

FF1

TO

FF8

8

9

8

9

13

14

17

18

12

15

16

19

13

14

17

18

12

15

16

19

13

14

17

18

12

15

16

19

MR

CP

1

MR

1

11

001aae055

mna764

mna763

Fig 1. Functional diagram

Fig 2. Logic symbol

Fig 3. IEC logic symbol

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

2 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

D0

D1

D2

D3

D

Q

D

Q

D

Q

D

Q

CP

FF1

FF2

FF3

FF4

R

D

R

D

R

D

CP

MR

Q0

Q1

Q2

Q3

D4

D5

D6

D7

D

Q

D

Q

D

Q

D

Q

CP

FF5

CP

FF6

CP

FF7

CP

FF8

R

D

R

D

R

D

R

D

Q4

Q5

Q6

Q7

001aae056

Fig 4. Logic diagram

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

3 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

5. Pinning information

5.1 Pinning

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ꢂꢆ

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ꢂꢂ

05

4ꢀ

9

&&

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4ꢃ

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&3

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'ꢀ

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4ꢄ

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ꢉ

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7UDQVSDUHQWꢊWRSꢊYLHZ

DDDꢀꢁꢁꢂꢁꢃꢃ

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration SO20 and TSSOP20

Fig 6. Pin configuration DHVQFN20

5.2 Pin description

Table 2.

Symbol

MR

Pin description

Description

1

master reset input (active LOW)

flip-flop output

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

2, 5, 6, 9, 12, 15, 16, 19

D0, D1, D2, D3, D4, D5, D6, D7

3, 4, 7, 8, 13, 14, 17, 18

data input

GND

CP

10

11

20

ground (0 V)

clock input (LOW-to-HIGH, edge-triggered)

supply voltage

V_CC

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

4 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

6. Functional description

Table 3.

Function table^[1]

Operating modes

Inputs

Outputs

MR

L

CP

X

Dn

X

h

Qn

L

reset (clear)

load “1”

H



H

load “0”

H



l

L

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;

 = LOW-to-HIGH clock transition.

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7

Unit

V

supply voltage

0.5

[1]

input clamping current

output clamping current

output current

V_I< 0.5 V or V_I> V_CC+ 0.5 V

V_O< 0.5 V or V_O> V_CC+ 0.5 V

0.5 V < V_O< V_CC+ 0.5 V

-

20

25

50

mA

C

I_OK

-

I_O

-

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

50

65

-

storage temperature

total power dissipation

+150

500

[2]

T_amb= 40 C to +125 C

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO20 package: above 70 C the value of P_totderates linearly with 8 mW/K.

For TSSOP20 package: above 60 C the value of P_totderates linearly with 5.5 mW/K.

For DHVQFN20 package: P_totderates linearly with 4.5 mW/K above 60 C.

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

5 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions

74HC273-Q100

74HCT273-Q100

Unit

Min

Typ

Max

Min

Typ

Max

V_CC

V_I

supply voltage

2.0

5.0

6.0

V_CC

+125

625

139

83

4.5

5.0

5.5

V_CC

V

input voltage

0

-

0

-

V_O

output voltage

0

-

0

-

T_amb

t/V

ambient temperature

input transition rise and fall rate V_CC= 2.0 V

V_CC= 4.5 V

40

-

40

-

+125 C

-

1.67

-

1.67

-

ns/V

139 ns/V

V_CC= 6.0 V

-

ns/V

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

74HC273-Q100

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

1.5

1.2

2.4

3.2

0.8

-

1.5

-

1.5

-

V

V_CC= 4.5 V

3.15

V_CC= 6.0 V

4.2

-

4.2

-

4.2

-

V_IL

LOW-level

input voltage

V_CC= 2.0 V

-

0.5

-

0.5

1.35

1.8

-

0.5

1.35

1.8

V_CC= 4.5 V

2.1 1.35

V_CC= 6.0 V

2.8

1.8

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

1.9

4.4

5.9

2.0

4.5

6.0

-

1.9

4.4

-

1.9

4.4

5.9

3.7

5.2

-

V

5.9

I_O= 4.0 mA; V_CC= 4.5 V 3.98 4.32

I_O= 5.2 mA; V_CC= 6.0 V 5.48 5.81

V_I= V_IHor V_IL

3.84

5.34

V_OL

LOW-level

output voltage

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

-

0

0.1

-

0.1

-

0.1

0.4

1

V

0.1

V

0.15 0.26

0.16 0.26

0.33

1

V

I_I

input leakage

current

V_I= V_CCor GND;

V_CC= 6.0 V

-

0.1

A

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

-

8.0

-

80

-

160

A

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

6 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

Table 6.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

C_I

input

-

3.5

-

pF

capacitance

74HCT273-Q100

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

1.6

1.2

-

2.0

-

2.0

-

V

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 A

4.4

4.5

-

4.4

-

4.4

3.7

-

V

I_O= 4.0 mA

3.98 4.32

3.84

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 A; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 5.5 V

-

0

0.1

-

0.1

0.33

1

-

0.1

0.4

1

V

0.15 0.26

V

I_I

input leakage

current

V_I= V_CCor GND;

V_CC= 5.5 V

-

0.1

A

I_CC

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

-

8.0

-

80

-

160

A

additional

supply current V_I= V_CC 2.1 V;

other inputs at V_CCor GND;

per input pin;

V_CC= 4.5 V to 5.5 V

MR input

-

100

175

15

360

630

54

-

450

787.5

67.5

-

490

A

CP input

857.5 A

Dn input

73.5

-

A

C_I

input

3.5

pF

capacitance

10. Dynamic characteristics

Table 7.

Dynamic characteristics

GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 10

Symbol Parameter

Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

74HC273-Q100

[1]

t_pd

propagation

delay

CP to Qn; see Figure 7

V_CC= 2.0 V

-

41 150

-

185

37

-

225

45

-

ns

V_CC= 4.5 V

15

13

30

-

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

26

31

38

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

7 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

Table 7.

Dynamic characteristics …continued

GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 10

Symbol Parameter

Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

t_PHL

HIGH to LOW

propagation

delay

MR to Qn; see Figure 8

V_CC= 2.0 V

-

44 150

-

185

37

-

225

45

-

ns

V_CC= 4.5 V

16

15

14

30

-

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

26

31

38

[2]

t_t

transition time

pulse width

Qn output; see Figure 7

V_CC= 2.0 V

-

19

7

75

15

13

-

95

19

15

-

110

22

ns

V_CC= 4.5 V

V_CC= 6.0 V

6

19

t_W

CP input HIGH or LOW;

see Figure 7

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

80

16

14

5

-

100

20

-

120

24

-

ns

4

17

20

MR input LOW;

see Figure 8

V_CC= 2.0 V

60

12

10

17

6

-

75

15

13

-

90

18

15

-

ns

V

_CC= 4.5 V

V_CC= 6.0 V

MR to CP; see Figure 8

V_CC= 2.0 V

5

t_rec

recovery time

set-up time

hold time

50

10

9

6

2

-

65

13

11

-

75

15

13

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

t_su

Dn to CP; see Figure 9

V_CC= 2.0 V

60

12

10

11

4

-

75

15

13

-

90

18

15

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

3

t_h

Dn to CP; see Figure 9

V_CC= 2.0 V

3

6

2

-

3

-

3

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

f_max

maximum

frequency

CP input; see Figure 7

V_CC= 2.0 V

6

20.6

-

4.8

24

-

4

20

-

MHz

pF

V_CC= 4.5 V

30 103

66

35 122

20

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

-

28

-

24

-

[3]

C_PD

power

per package;

-

dissipation

capacitance

V_I= GND to V_CC

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

8 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

Table 7.

Dynamic characteristics …continued

GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 10

Symbol Parameter

Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

74HCT273-Q100

[1]

t_pd

propagation

delay

CP to Qn; see Figure 7

V_CC= 4.5 V

-

16

15

30

-

38

-

45

-

ns

V_CC= 5.0 V; C_L= 15 pF

MR to Qn; see Figure 8

V_CC= 4.5 V

t_PHL

HIGH to LOW

propagation

delay

-

23

20

34

-

43

-

51

-

ns

V_CC= 5.0 V; C_L= 15 pF

Qn output; see Figure 7

V_CC= 4.5 V

[2]

t_t

transition time

pulse width

-

7

9

15

-

19

-

22

-

ns

t_W

CP input; see Figure 7

V_CC= 4.5 V

16

20

24

MR input LOW;

see Figure 8

V_CC= 4.5 V

16

10

12

3

8

2

5

-

20

13

15

3

-

24

15

18

3

-

ns

t_rec

recovery time

set-up time

hold time

MR to CP; see Figure 8

V_CC= 4.5 V

t_su

Dn to CP; see Figure 9

V_CC= 4.5 V

t_h

Dn to CP; see Figure 9

V_CC= 4.5 V

4

f_max

maximum

frequency

CP input; see Figure 7

V_CC= 4.5 V

30

-

56

36

23

-

24

-

20

-

MHz

pF

V_CC= 5.0 V; C_L= 15 pF

[3]

C_PD

power

per package;

-

dissipation

capacitance

V_I= GND to V_CC 1.5 V

[1] t_pdis the same as t_PHLand t_PLH

.

[2] t_tis the same as t_THLand t_TLH

.

[3]

C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i+ (C_L V_CC² f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

 (C_L V_CC² f_o) = sum of outputs;

C_L= output load capacitance in pF;

V_CC= supply voltage in V.

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

9 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

11. Waveforms

1/f

max

V

I

CP input

V

t

V

t

M

GND

t

W

PHL

PLH

V

OH

90%

V

Qn output

M

10%

V

OL

t

TLH

001aae062

THL

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 7. Propagation delay clock input (CP) to output (Qn), clock (CP) pulse width, output transition time and the

maximum clock pulse frequency

V

I

V

MR input

M

GND

t

rec

W

V

I

CP input

V

M

GND

t

PHL

V

OH

V

Qn output

M

V

OL

mna464

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 8. Propagation delay master reset (MR) to output (Qn), pulse width master reset (MR) and recovery time

master reset (MR) to clock (CP)

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

10 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

V

I

V

M

CP input

GND

t

su

t

h

V

I

V

Dn input

M

GND

V

OH

V

Qn output

M

V

OL

mna767

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 9. Data set-up and hold times data input (Dn)

Table 8.

Type

Measurement points

Input

Output

V_M

V_I

V_M

74HC273-Q100

74HCT273-Q100

V_CC

3 V

0.5V_CC

1.3 V

0.5V_CC

1.3 V

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

11 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

CC

V

O

I

R

L

S1

G

open

DUT

R

T

C

L

001aad983

Test data is given in Table 9.

Definitions for test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

R_L= Load resistance.

S1 = Test selection switch

Fig 10. Test circuit for measuring switching times

Table 9.

Type

Test data

Input

V_I

Load

S1 position

t_PHL, t_PLH

open

t_r, t_f

6 ns

C_L

R_L

74HC273-Q100

74HCT273-Q100

V_CC

3 V

15 pF, 50 pF

1 k

open

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

12 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

12. Package outline

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig 11. Package outline SOT163-1 (SO20)

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

13 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig 12. Package outline SOT360-1 (TSSOP20)

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

14 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

SOT764-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

9

L

1

10

E

h

e

20

11

19

12

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

1

y

D

E

L

v

w

y

1

h

max.

0.05 0.30

0.00 0.18

4.6

4.4

3.15

2.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT764-1

- - -

MO-241

- - -

Fig 13. Package outline SOT764-1 (DHVQFN20)

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

15 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

13. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Military

ESD

HBM

MIL

MM

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date

20130619

Data sheet status

Change notice

Supersedes

74HC_HCT273_Q100 v.1

Product data sheet

-

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

16 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

15.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

17 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74HC_HCT273_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 June 2013

18 of 19

74HC273-Q100; 74HCT273-Q100

NXP Semiconductors

Octal D-type flip-flop with reset; positive-edge trigger

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 June 2013

Document identifier: 74HC_HCT273_Q100


型号：	74HCT273D-Q100
厂家：	NXP
描述：	Octal D-type flip-flop with reset; positive-edge trigger 八路D型触发器与复位;正边沿触发触发器
文件：	总19页 (文件大小：147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HCT273D-Q100 [NXP]

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