74HCT27 [NXP]
Triple 3-input NOR gate; 三路3输入NOR门
| 型号： | 74HCT27 |
| 厂家： | 
NXP |
| 描述： | Triple 3-input NOR gate |
| 文件： | 总5页 (文件大小：37K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT27
Triple 3-input NOR gate
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Triple 3-input NOR gate
74HC/HCT27
FEATURES
GENERAL DESCRIPTION
• Output capability: standard
• ICC category: SSI
The 74HC/HCT27 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT27 provide the 3-input NOR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
HC
HCT
10
tPHL/ tPLH
CI
propagation delay nA, nB, nC to nY
input capacitance
CL = 15 pF; VCC = 5 V
8
3.5
24
3.5
30
pF
pF
CPD
power dissipation capacitance per gate
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fO) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Triple 3-input NOR gate
74HC/HCT27
PIN DESCRIPTION
PIN NO.
1, 3, 9
2, 4, 10
13, 5, 11
7
SYMBOL
1A to 3A
1B to 3B
1C to 3C
GND
NAME AND FUNCTION
data inputs
data inputs
data inputs
ground (0 V)
12, 6, 8
14
1Y to 3Y
VCC
data outputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS
nB
OUTPUT
nY
nA
nC
L
X
X
H
L
X
H
X
L
H
X
X
H
L
L
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Fig.4 Functional diagram.
Fig.5 Logic diagram (one gate).
December 1990
3
Philips Semiconductors
Product specification
Triple 3-input NOR gate
74HC/HCT27
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA, nB, nC to nY
28
10
8
90
18
15
115
23
20
135
27
23
ns
2.0
4.5
6.0
Fig.6
Fig.6
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
December 1990
4
Philips Semiconductors
Product specification
Triple 3-input NOR gate
74HC/HCT27
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
nA, nB, nC
1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA, nB, nC to nY
12
7
21
15
26
19
32
22
ns
ns
4.5
4.5
Fig.6
Fig.6
t
THL/ tTLH output transition time
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
5
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