74HCT2G00DP [NXP]
Dual 2-input NAND gate; 双路2输入与非门
| 型号： | 74HCT2G00DP |
| 厂家： | 
NXP |
| 描述： | Dual 2-input NAND gate |
| 文件： | 总16页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74HC2G00; 74HCT2G00
Dual 2-input NAND gate
Product specification
2003 Feb 12
Supersedes data of 2002 Jul 10
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
FEATURES
DESCRIPTION
• Wide supply voltage range from 2.0 to 6.0 V
• Symmetrical output impedance
• High noise immunity
The 74HC2G/HCT2G00 is a high-speed Si-gate CMOS
device.
The 74HC2G/HCT2G00 provides the 2-input NAND
function.
• Low power dissipation
• Balanced propagation delays
• Very small 8 pins package
• Output capability is standard
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC2G00
HCT2G00
12
tPHL/tPLH propagation delay nA, nB to nY
CL = 50 pF; VCC = 4.5 V
9
ns
pF
pF
CI
input capacitance
power dissipation capacitance per gate notes 1 and 2
1.5
10
1.5
10
CPD
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
N = total load switching outputs;
VCC = supply voltage in Volts;
∑ (CL × VCC2 × fo) = sum of outputs.
2. For 74HC2G00 the condition is VI = GND to VCC
.
For 74HCT2G00 the condition is VI = GND to VCC − 1.5 V.
2003 Feb 12
2
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nY
nA
nB
L
L
L
H
L
H
H
H
L
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PACKAGE MATERIAL
TEMPERATURE
RANGE
PINS
CODE
MARKING
74HC2G00DP
74HCT2G00DP
74HC2G00DC
74HCT2G00DC
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
8
8
8
8
TSSOP8
TSSOP8
VSSOP8
VSSOP8
plastic
plastic
plastic
plastic
SOT505-2
SOT505-2
SOT765-1
SOT765-1
P00
U00
P00
U00
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
3
4
5
6
7
8
1A
data input 1A
data input 1B
data output 2Y
ground (0 V)
data input 2A
data input 2B
data output 1Y
supply voltage
1B
2Y
GND
2A
2B
1Y
VCC
2003 Feb 12
3
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
handbook, halfpage
1A
1B
1
2
3
4
8
7
6
5
V
CC
handbook, halfpage
1
2
1A
1B
1Y
2Y
7
3
1Y
2B
2A
00
5
6
2A
2B
2Y
GND
MNA712
MNA711
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1
handbook, halfpage
&
&
7
3
2
handbook, halfpage
B
A
Y
5
6
MNA099
MNA713
Fig.3 IEC logic symbol.
Fig.4 Logic diagram (one driver).
2003 Feb 12
4
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
RECOMMENDED OPERATING CONDITIONS
74HC2G00
74HCT2G00
UNIT
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
2.0
TYP. MAX. MIN.
TYP. MAX.
VCC
VI
5.0
−
6.0
4.5
0
5.0
5.5
V
V
V
input voltage
0
VCC
VCC
−
VCC
VCC
VO
output voltage
0
−
0
−
Tamb
operating ambient
temperature
see DC and AC
characteristics per
device
−40
+25
+125 −40
+25
+125 °C
tr, tf
input rise and fall times
VCC = 2.0 V
VCC = 4.5 V
−
−
−
−
1000
500
−
−
−
−
−
ns
ns
ns
6.0
−
6.0
−
500
−
VCC = 6.0 V
400
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
IIK
−0.5
−
+7.0
±20
±20
25
V
input diode current
VI < −0.5 V or VI > VCC + 0.5 V; note 1
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−0.5 V < VO < VCC + 0.5 V; note 1
note 1
mA
mA
mA
mA
IOK
IO
output diode current
−
output source or sink current
VCC or GND current
−
ICC
Tstg
PD
−
50
storage temperature
−65
−
+150 °C
300 mW
power dissipation per package
for temperature range from −40 to +125 °C;
note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 110 °C the value of PD derates linearly with 8 mW/K.
2003 Feb 12
5
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
DC CHARACTERISTICS
Type 74HC2G00
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); note 1.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input
2.0
4.5
6.0
2.0
4.5
6.0
1.5
1.2
−
−
−
V
voltage
3.15
4.2
−
2.4
3.2
0.8
2.1
2.8
V
V
V
V
V
VIL
LOW-level input voltage
0.5
−
1.35
1.8
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −20 µA
IO = −20 µA
2.0
4.5
6.0
4.5
6.0
1.9
2.0
−
−
−
−
−
V
V
V
V
V
4.4
4.5
IO = −20 µA
5.9
6.0
IO = −4.0 mA
IO = −5.2 mA
VI = VIH or VIL
IO = 20 µA
4.13
5.63
4.32
5.81
VOL
LOW-level output
voltage
2.0
4.5
6.0
4.5
6.0
6.0
6.0
−
−
−
−
−
−
−
0
0.1
V
IO = 20 µA
0
0.1
V
IO = 20 µA
0
0.1
V
IO = 4.0 mA
0.15
0.16
−
0.33
0.33
±1.0
10
V
IO = 5.2 mA
V
ILI
input leakage current
VI = VCC or GND
VI = VCC or GND; IO = 0
µA
µA
ICC
quiescent supply
current
−
2003 Feb 12
6
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
TEST CONDITIONS
OTHER
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +125 °C
VIH HIGH-level input
2.0
4.5
6.0
2.0
4.5
6.0
1.5
−
−
−
−
−
−
−
−
−
V
voltage
3.15
4.2
−
V
V
V
V
V
VIL
LOW-level input voltage
0.5
−
1.35
1.8
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −20 µA
IO = −20 µA
2.0
4.5
6.0
4.5
6.0
1.9
4.4
5.9
3.7
5.2
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
IO = −20 µA
IO = −4.0 mA
IO = −5.2 mA
VI = VIH or VIL
IO = 20 µA
VOL
LOW-level output
voltage
2.0
4.5
6.0
4.5
6.0
6.0
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.1
0.1
0.1
0.4
0.4
±1.0
20
V
IO = 20 µA
V
IO = 20 µA
V
IO = 4.0 mA
V
IO = 5.2 mA
V
ILI
input leakage current
VI = VCC or GND
VI = VCC or GND; IO = 0
µA
µA
ICC
quiescent supply
current
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Feb 12
7
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
Type 74HCT2G00
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); note 1.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH
VIL
HIGH-level input
voltage
4.5 to 5.5
4.5 to 5.5
2.0
1.6
−
V
LOW-level input
voltage
−
1.2
0.8
V
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −20 µA
4.5
4.5
4.4
4.5
−
−
V
V
IO = −4.0 mA
VI = VIH or VIL
IO = 20 µA
4.13
4.32
VOL
LOW-level output
voltage
4.5
4.5
5.5
5.5
−
−
−
−
0
0.1
V
IO = 4.0 mA
0.15
−
0.33
±1.0
10
V
ILI
input leakage current
VI = VCC or GND
µA
µA
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
−
∆ICC
additional supply
current per input
VI = VCC − 2.1 V; IO = 0 4.5 to 5.5
−
−
375
µA
Tamb = −40 to +125 °C
VIH
HIGH-level input
voltage
4.5 to 5.5
4.5 to 5.5
2.0
−
−
−
V
V
VIL
LOW-level input
voltage
−
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −20 µA
IO = −4.0 mA
VI = VIH or VIL
IO = 20 µA
4.5
4.5
4.4
3.7
−
−
−
−
V
V
VOL
LOW-level output
voltage
4.5
4.5
5.5
5.5
−
−
−
−
0.1
0.4
±1.0
20
V
IO = 4.0 mA
−
−
−
V
ILI
input leakage current
VI = VCC or GND
µA
µA
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
∆ICC
additional supply
current per input
VI = VCC − 2.1 V; IO = 0 4.5 to 5.5
−
−
410
µA
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Feb 12
8
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
AC CHARACTERISTICS
Type 74HC2G00
GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF; note 1.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C
tPHL/tPLH
propagation delay nA,
nB to nY
see Figs 5 and 6
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
25
95
ns
9
19
16
95
19
16
ns
ns
ns
ns
ns
7
t
THL/tTLH
output transition time
see Figs 5 and 6
18
6
5
T
amb = −40 to +125 °C
tPHL/tPLH
propagation delay nA,
nB to nY
see Figs 5 and 6
see Figs 5 and 6
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
−
−
−
−
−
−
110
22
ns
ns
ns
ns
ns
ns
20
t
THL/tTLH
output transition time
125
25
20
Note
1. All typical values are measured at Tamb = 25 °C.
Type 74HCT2G00
GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF; note 1.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C
t
PHL/tPLH
THL/tTLH
propagation delay nA,
nB to nY
see Figs 5 and 6
see Figs 5 and 6
4.5
4.5
−
−
12
6
24
19
ns
ns
t
output transition time
Tamb = −40 to +125 °C
tPHL/tPLH propagation delay nA,
see Figs 5 and 6
see Figs 5 and 6
4.5
4.5
−
−
−
−
29
22
ns
ns
nB to nY
t
THL/tTLH
output transition time
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Feb 12
9
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
AC WAVEFORMS
V
handbook, halfpage
I
V
V
M
nA, nB input
M
GND
t
t
PHL
PLH
V
OH
90%
V
V
nY output
M
M
10%
V
OL
t
t
TLH
MNA714
THL
For 74HC2G00: VM = 50%; VI = GND to VCC
.
For 74HCT2G00: VM = 1.3 V; VI = GND to 3.0 V.
Fig.5 The input (nA, nB) to output (nY) propagation delays and transition times.
S1
V
CC
open
V
CC
GND
R
L
1 kΩ
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
50 pF
L
R
T
MNA742
TEST
S1
t
PLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
open
Vcc
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
GND
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2003 Feb 12
10
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
PACKAGE OUTLINES
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
2003 Feb 12
11
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.12
0.5
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
2003 Feb 12
12
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferably be kept:
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 220 °C for all the BGA packages and packages
with a thickness ≥ 2.5mm and packages with a
thickness <2.5 mm and a volume ≥350 mm3 so called
thick/large packages
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
• below 235 °C for packages with a thickness <2.5 mm
and a volume <350 mm3 so called small/thin packages.
Wave soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 Feb 12
13
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
WAVE
REFLOW(2)
not suitable suitable
PACKAGE(1)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
suitable
PLCC(4), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(4)(5) suitable
not recommended(6)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Feb 12
14
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74HC2G00; 74HCT2G00
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Feb 12
15
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/02/pp16
Date of release: 2003 Feb 12
Document order number: 9397 750 10563
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