74HCT2G86 [NXP]
Dual 2-input exclusive-OR gate; 双2输入异或门型号: | 74HCT2G86 |
厂家: | NXP |
描述: | Dual 2-input exclusive-OR gate |
文件: | 总17页 (文件大小:84K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74HC2G86; 74HCT2G86
Dual 2-input exclusive-OR gate
Product specification
2003 Jul 28
Supersedes data of 2002 Jul 17
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
FEATURES
DESCRIPTION
• Wide supply voltage range from 2.0 to 6.0 V
• Symmetrical output impedance
• High noise immunity
The 74HC2G/HCT2G86 is a high-speed Si-gate CMOS
device.
The 74HC2G/HCT2G86 provides dual 2-input
exclusive-OR gate.
• Low power dissipation
• Balanced propagation delays
• Very small 8 pins package
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC2G86 HCT2G86
tPHL/tPLH propagation delay nA to nY
CL = 50 pF; VCC = 4.5 V 11
1.5
11
1.5
9
ns
pF
pF
CI
input capacitance
CPD
power dissipation capacitance per gate notes 1 and 2
10
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
∑ (CL × VCC2 × fo) = sum of outputs.
2. For 74HC2G86 the condition is VI = GND to VCC
.
For 74HCT2G86 the condition is VI = GND to VCC − 1.5 V.
2003 Jul 28
2
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nY
nA
nA
L
L
L
H
L
L
H
H
L
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
PACKAGE
PACKAGE MATERIAL
TYPE NUMBER
TEMPERATURE
PINS
CODE
MARKING
RANGE
74HC2G86DP
74HCT2G86DP
74HC2G86DC
74HCT2G86DC
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
8
8
8
8
TSSOP8
TSSOP8
VSSOP8
VSSOP8
plastic
plastic
plastic
plastic
SOT505-2
SOT505-2
SOT765-1
SOT765-1
H86
T86
H86
H86
PINNING
PIN
1
SYMBOL
DESCRIPTION
1A
1B
2Y
data input 1A
data input 1B
data output 2Y
ground (0 V)
data input 2A
data input 2B
data output 1Y
supply voltage
2
3
4
GND
2A
5
6
2B
7
1Y
8
VCC
2003 Jul 28
3
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
handbook, halfpage
1A
1B
1
2
3
4
8
7
6
5
V
CC
handbook, halfpage
1
2
1A
1B
1Y
2Y
7
3
1Y
2B
2A
86
5
6
2A
2B
2Y
GND
MNA737
MNA736
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1
handbook, halfpage
= 1
= 1
7
3
handbook, halfpage
B
2
Y
5
6
A
MNA040
MNA738
Fig.3 IEC logic symbol.
Fig.4 Logic diagram (one driver).
2003 Jul 28
4
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
RECOMMENDED OPERATING CONDITIONS
74HC2G86
74HCT2G86
UNIT
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
2.0
TYP. MAX. MIN.
TYP. MAX.
VCC
VI
5.0
−
6.0
4.5
0
5.0
5.5
V
V
V
input voltage
0
VCC
VCC
−
VCC
VCC
VO
output voltage
0
−
0
−
Tamb
operating ambient
temperature
see DC and AC
characteristics per
device
−40
+25
+125 −40
+25
+125 °C
tr, tf
input rise and fall times
VCC = 2.0 V
VCC = 4.5 V
−
−
−
−
1000
500
−
−
−
−
−
ns
ns
ns
6.0
−
6.0
−
500
−
VCC = 6.0 V
400
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
IIK
−0.5
−
+7.0
±20
±20
25
V
input diode current
VI < −0.5 V or VI > VCC + 0.5 V; note 1
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−0.5 V < VO < VCC + 0.5 V; note 1
note 1
mA
mA
mA
mA
IOK
IO
output diode current
output source or sink current
VCC or GND current
storage temperature
power dissipation
−
−
ICC
Tstg
PD
−
50
−65
−
+150 °C
300 mW
Tamb = −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 110 °C the value of PD derates linearly with 8 mW/K.
2003 Jul 28
5
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
DC CHARACTERISTICS
Type 74HC2G86
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = 25 °C
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
1.2
−
V
3.15
4.2
−
2.4
3.2
0.8
2.1
2.8
−
V
V
V
V
V
−
VIL
0.5
1.35
1.8
−
−
VOH
VI = VIH or VIL
IO = −20 µA
IO = −20 µA
IO = −20 µA
IO = −4.0 mA
IO = −5.2 mA
VI = VIH or VIL
IO = 20 µA
2.0
4.5
6.0
4.5
6.0
1.9
2.0
−
−
−
−
−
V
V
V
V
V
4.4
4.5
5.9
6.0
4.18
5.68
4.32
5.81
VOL
LOW-level output voltage
2.0
4.5
6.0
4.5
6.0
6.0
6.0
−
−
−
−
−
−
−
0
0.1
V
IO = 20 µA
0
0.1
V
IO = 20 µA
0
0.1
V
IO = 4.0 mA
IO = 5.2 mA
VI = VCC or GND
0.15
0.16
−
0.26
0.26
±0.1
1.0
V
V
ILI
input leakage current
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
−
2003 Jul 28
6
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
−
−
−
−
−
−
−
V
3.15
4.2
−
−
V
V
V
V
V
−
VIL
LOW-level input voltage
HIGH-level output voltage
0.5
1.35
1.8
−
−
VOH
VI = VIH or VIL
IO = −20 µA
IO = −20 µA
IO = −20 µA
IO = −4.0 mA
IO = −5.2 mA
VI = VIH or VIL
IO = 20 µA
2.0
4.5
6.0
4.5
6.0
1.9
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
4.4
5.9
4.13
5.63
VOL
LOW-level output voltage
2.0
4.5
6.0
4.5
6.0
6.0
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
IO = 20 µA
0.1
V
IO = 20 µA
0.1
V
IO = 4.0 mA
IO = 5.2 mA
VI = VCC or GND
0.33
0.33
±1.0
10
V
V
ILI
input leakage current
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
2003 Jul 28
7
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +125 °C
VIH HIGH-level input voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
−
−
−
−
−
−
−
V
3.15
4.2
−
−
V
V
V
V
V
−
VIL
LOW-level input voltage
HIGH-level output voltage
0.5
1.35
1.8
−
−
VOH
VI = VIH or VIL
IO = −20 µA
IO = −20 µA
IO = −20 µA
IO = −4.0 mA
IO = −5.2 mA
VI = VIH or VIL
IO = 20 µA
2.0
4.5
6.0
4.5
6.0
1.9
4.4
5.9
3.7
5.2
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
VOL
LOW-level output voltage
2.0
4.5
6.0
4.5
6.0
6.0
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.1
0.1
0.1
0.4
0.4
±1.0
20
V
IO = 20 µA
V
IO = 20 µA
V
IO = 4.0 mA
IO = 5.2 mA
VI = VCC or GND
V
V
ILI
input leakage current
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
2003 Jul 28
8
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
Type 74HCT2G86
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = 25 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
4.5 to 5.5
4.5 to 5.5
2.0
1.6
−
V
−
1.2
0.8
V
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA
4.5
4.5
4.4
4.5
−
−
V
V
IO = −4.0 mA
4.18
4.32
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA
4.5
4.5
5.5
5.5
−
−
−
−
0
0.1
V
IO = 4.0 mA
0.15
−
0.26
±0.1
1.0
V
ILI
input leakage current
VI = VCC or GND
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
−
∆ICC
additional supply current
per input
VI = VCC − 2.1 V;
IO = 0
4.5 to 5.5
−
−
300
µA
Tamb = −40 to +85 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
4.5 to 5.5
4.5 to 5.5
2.0
−
−
−
V
V
−
0.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA
4.5
4.5
4.4
−
−
−
−
V
V
IO = −4.0 mA
4.13
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA
4.5
4.5
5.5
5.5
−
−
−
−
−
−
−
−
0.1
V
IO = 4.0 mA
0.33
±1.0
10
V
ILI
input leakage current
VI = VCC or GND
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
∆ICC
additional supply current
per input
VI = VCC − 2.1 V;
IO = 0
4.5 to 5.5
−
−
375
µA
2003 Jul 28
9
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
TEST CONDITIONS
OTHER CC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
Tamb = −40 to +125 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
4.5 to 5.5
4.5 to 5.5
2.0
−
−
−
V
−
0.8
V
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA
4.5
4.5
4.4
3.7
−
−
−
−
V
V
IO = −4.0 mA
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA
4.5
4.5
5.5
5.5
−
−
−
−
−
−
−
−
0.1
0.4
±1.0
20
V
IO = 4.0 mA
V
ILI
input leakage current
VI = VCC or GND
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
∆ICC
additional supply current
per input
VI = VCC − 2.1 V;
IO = 0
4.5 to 5.5
−
−
410
µA
2003 Jul 28
10
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
AC CHARACTERISTICS
Type 74HC2G86
GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL
PARAMETER
propagation delay nA, nB to nY
output transition time
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = 25 °C
tPHL/tPLH
see Figs 5 and 6
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
34
120
ns
11
9
20
17
75
15
13
ns
ns
ns
ns
ns
t
THL/tTLH
see Figs 5 and 6
18
6
5
Tamb = −40 to +85 °C
tPHL/tPLH
propagation delay nA, nB to nY
see Figs 5 and 6
see Figs 5 and 6
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
−
−
−
−
−
−
150
25
21
95
19
16
ns
ns
ns
ns
ns
ns
t
THL/tTLH
output transition time
T
amb = −40 to +125 °C
tPHL/tPLH
propagation delay nA, nB to nY
see Figs 5 and 6
see Figs 5 and 6
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
−
−
−
−
−
−
180
36
ns
ns
ns
ns
ns
ns
30
t
THL/tTLH
output transition time
110
22
20
2003 Jul 28
11
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
Type 74HCT2G86
GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = 25 °C
tPHL/tPLH
propagation delay nA, nB to nY
output transition time
see Figs 5 and 6
see Figs 5 and 6
4.5
4.5
−
−
11
19
ns
tTHL/tTLH
6
15
ns
Tamb = −40 to +85 °C
tPHL/tPLH propagation delay nA, nB to nY
tTHL/tTLH output transition time
Tamb = −40 to +125 °C
tPHL/tPLH propagation delay nA, nB to nY
THL/tTLH output transition time
see Figs 5 and 6
see Figs 5 and 6
4.5
4.5
−
−
−
−
23
19
ns
ns
see Figs 5 and 6
see Figs 5 and 6
4.5
4.5
−
−
−
−
48
22
ns
ns
t
AC WAVEFORMS
V
handbook, halfpage
I
V
V
M
nA, nB input
M
GND
t
t
PHL
PLH
V
OH
90%
V
V
nY output
M
M
10%
V
OL
t
t
TLH
MNA726
THL
For HC2G: VM = 50%; VI = GND to VCC
.
For HCT2G: VM = 1.3 V; VI = GND to 3.0 V.
Fig.5 The input (nA, nB) to output (nY) propagation delays.
2003 Jul 28
12
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
S1
V
CC
open
V
CC
GND
R
=
L
1 kΩ
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
50 pF
=
L
R
T
MNA742
TEST
PLH/tPHL
PLZ/tPZL
S1
Definitions for test circuit:
L = Load resistor.
CL = Load capacitance including jig and probe capacitance.
t
t
open
VCC
R
tPHZ/tPZH
GND
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2003 Jul 28
13
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
PACKAGE OUTLINES
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.25
0.65
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
2003 Jul 28
14
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
2003 Jul 28
15
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jul 28
16
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/02/pp17
Date of release: 2003 Jul 28
Document order number: 9397 750 10567
相关型号:
74HCT2G86DC-Q100
HCT SERIES, DUAL 2-INPUT XOR GATE, PDSO8, 2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8
NXP
©2020 ICPDF网 联系我们和版权申明