74HCT30PW [NXP]
8-input NAND gate; 8输入与非门
| 型号： | 74HCT30PW |
| 厂家： | 
NXP |
| 描述： | 8-input NAND gate |
| 文件： | 总6页 (文件大小：38K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT30
8-input NAND gate
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-input NAND gate
74HC/HCT30
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT30 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT30 provide the 8-input NAND function.
QUICK REFERENEC DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
HC
12
HCT
12
tPHL/ tPLH
CI
propagation delay A, B, C, D, E, F, G, H to Y
input capacitance
CL = 15 pF; VCC = 5 V
3.5
15
3.5
15
pF
pF
CPD
power dissipation capacitance per gate
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
2
PD = CPD × VCC × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
8-input NAND gate
74HC/HCT30
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
2
3
4
5
6
7
8
A
data input
B
data input
C
data input
D
data input
E
data input
F
data input
GND
Y
ground (0 V)
data output
not connected
data input
9, 10, 13
n.c.
G
11
12
14
H
data input
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-input NAND gate
74HC/HCT30
Fig.4 Functional diagram;
Y = ABCDEFGH.
Fig.5 Logic diagram.
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
C
D
E
F
G
H
L
X
X
X
X
L
X
X
X
X
L
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L
X
X
X
X
L
X
X
X
L
H
H
H
H
X
H
H
H
H
H
H
H
H
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
December 1990
4
Philips Semiconductors
Product specification
8-input NAND gate
74HC/HCT30
DC CHARACTERISTICS FOR 74 HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
+25
−40 to + 85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
A, B, C, D, E, F, G, H to Y
41 130
15 26
12 22
165
33
28
195
39
33
ns
ns
2.0 Fig.6
4.5
6.0
t
THL/ tTLH output transition time
19 75
95
19
16
110
22
19
2.0 Fig.6
4.5
6.0
7
6
15
13
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
A, B, C, D, E, F, G, H 0.60
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
−40
to +125
VCC
+25
−40 to + 85
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
A, B, C, D, E, F, G, H to Y
16
28
35
42
ns
ns
4.5 Fig.6
4.5 Fig.6
tTHL/ tTLH output transition time
7
15
19
22
December 1990
5
Philips Semiconductors
Product specification
8-input NAND gate
74HC/HCT30
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input (A, B, C, D, E, F, G, H) to output (Y) propagation delays and the output
transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
6
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