74HCT32 [SLS]

Quad 2-Input OR Gate(High-Performance Silicon-Gate CMOS); 四2输入或门（高性能硅栅CMOS ）


型号：	74HCT32
厂家：	SYSTEM LOGIC SEMICONDUCTOR
描述：	Quad 2-Input OR Gate(High-Performance Silicon-Gate CMOS) 四2输入或门（高性能硅栅CMOS ）栅
文件：	总4页 (文件大小：38K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SL74HCT32

Quad 2-Input OR Gate

High-Performance Silicon-Gate CMOS

The SL74HCT32 may be used as a level converter for interfacing

TTL or NMOS outputs to High-Speed CMOS inputs.

The SL74HCT32 is identical in pinout to the LS/ALS32.

TTL/NMOS-Compatible Input Levels.

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 4.5 to 5.5 V

Low Input Current: 1.0 mA

ORDERING INFORMATION

SL74HCT32N Plastic

SL74HCT32D SOIC

T_A= -55° to 125° C for all packages

LOGIC DIAGRAM

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Output

PIN 14 =V_CC

PIN 7 = GND

System Logic

SLS

Semiconductor

SL74HCT32

MAXIMUM RATINGS^*

Symbol

Parameter

Value

-0.5 to +7.0

-1.5 to V_CC+1.5

-0.5 to V_CC+0.5

±20

Unit

V_CC

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

DC Input Current, per Pin

V_OUT

I_IN

I_OUT

I_CC

DC Output Current, per Pin

±25

DC Supply Current, V_CCand GND Pins

±50

P_D

Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750

500

Tstg

T_L

Storage Temperature

-65 to +150

260

°C

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

^*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

V_CC

Parameter

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

Input Rise and Fall Time (Figure 1)

Min

4.5

Max

5.5

Unit

V , V_OUT

V_CC

T_A

-55

+125

500

°C

t_r, t_f

This device contains protection circuitry to guard against damage due to high static voltages or electric

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, V and V_OUTshould be constrained to the range

GND£(V or V_OUT)£V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).

Unused outputs must be left open.

System Logic

SLS

Semiconductor

SL74HCT32

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

V_CC

Guaranteed Limit

Symbol

Parameter

Test Conditions

25 °C

£85

°C

£125

°C

Unit

-55°C

Minimum High-Level

Input Voltage

V_OUT= V_CC-0.1 V

êI_OUTê£ 20 mA

4.5

5.5

2.0

Maximum Low -Level

Input Voltage

V_OUT=0.1 V or V_CC-0.1 V

êI_OUTê £ 20 mA

4.5

5.5

0.8

V_OH

Minimum High-Level

Output Voltage

V =V or V

4.5

5.5

4.4

5.4

4.4

5.4

4.4

5.4

êI_OUTê £ 20 mA

V =V or V

êI_OUTê £ 4.0 mA

êI_OUTê £ 5.2 mA

4.5

3.98

3.84

3.7

V_OL

Maximum Low-Level

Output Voltage

V = V

êI_OUTê £ 20 mA

4.5

5.5

0.1

V = V

êI_OUTê £ 4.0 mA

êI_OUTê £ 5.2 mA

4.5

5.5

0.26

±0.1

1.0

0.33

±1.0

0.4

±1.0

I_IN

Maximum Input

Leakage Current

V =V_CCor GND

I_CC

Maximum Quiescent

Supply Current

(per Package)

V =V_CCor GND

I_OUT=0mA

DI_CC

Additional Quiescent V =2.4 V, Any One Input

Supply Current

³ -55° C

25°C to

125 °C

V =V_CCor GND,

5.5

2.9

2.4

Other Input

I_OUT= 0 mA

System Logic

Semiconductor

SLS

SL74HCT32

AC ELECTRICAL CHARACTERISTICS(V_CC=5.0 V ± 10%, C_L=50pF,Input t_r=t_f=6.0 ns)

Guaranteed Limits

Symbol

Parameter

25 °C to

-55°C

£85°C

£125°C

Unit

t_PLH, t_PHLMaximum Propagation Delay, Input A or B

to Output Y (Figures 1 and 2)

t_TLH, t_THLMaximum Output Transition Time, Any

Output (Figures 1 and 2)

C_IN

Maximum Input Capacitance

Power Dissipation Capacitance (Per Gate)

Typical @25°C,V_CC=5.0 V

C_PD

Used to determine the no-load dynamic

power consumption:

P_D=C_PDV_CC²f+I_CCV_CC

Figure 1 Switching Waveforms.

Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM

(1/4 of the Device)

System Logic

Semiconductor

SLS

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