74HCT32N [NXP]

Quad 2-input OR gate; 四2输入或门


型号：	74HCT32N
厂家：	NXP
描述：	Quad 2-input OR gate 四2输入或门栅极触发器逻辑集成电路光电二极管
文件：	总6页 (文件大小：39K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT32

Quad 2-input OR gate

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Quad 2-input OR gate

74HC/HCT32

FEATURES

GENERAL DESCRIPTION

• Output capability: standard

• I_CCcategory: SSI

The 74HC/HCT32 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT32 provide the 2-input OR function.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

t_PHL/ t_PLH

PARAMETER

CONDITIONS

UNIT

HC HCT

propagation delay nA, nB to nY

input capacitance

C_L= 15 pF; V_CC= 5 V

C_I

3.5 3.5

C_PD

power dissipation capacitance per gate

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC× f_i+ ∑ (C_L× V_CC× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors

Product speciﬁcation

Quad 2-input OR gate

74HC/HCT32

PIN DESCRIPTION

PIN NO.

1, 4, 9, 12

SYMBOL

NAME AND FUNCTION

1A to 4A

1B to 4B

1Y to 4Y

GND

data inputs

2, 5, 10, 13

data inputs

3, 6, 8, 11

data outputs

ground (0 V)

V_CC

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

Quad 2-input OR gate

74HC/HCT32

FUNCTION TABLE

INPUTS

OUTPUT

Notes

1. H = HIGH voltage level

L = LOW voltage level

Fig.4 Functional diagram.

Fig.5 Logic diagram 74HC (one gate).

Fig.6 Logic diagram 74HCT (one gate).

December 1990

Philips Semiconductors

Product speciﬁcation

Quad 2-input OR gate

74HC/HCT32

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: SSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

_amb(°C)

TEST CONDITIONS

74HC

SYMBOL

PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

nA, nB to nY

115

135

2.0 Fig.7

4.5

6.0

_THL/ t_TLHoutput transition time

110

2.0 Fig.7

4.5

6.0

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: SSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

nA, nB

1.20

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

_amb(°C)

TEST CONDITIONS

V_CC

74HCT

SYMBOL

PARAMETER

UNIT

WAVEFORMS

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

nA, nB to nY

4.5 Fig.7

_THL/ t_TLHoutput transition time

December 1990

Philips Semiconductors

Product speciﬁcation

Quad 2-input OR gate

74HC/HCT32

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.7 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

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