74HCT40103DB [NXP]
8-bit synchronous binary down counter; 8位同步二进制可逆计数器
| 型号： | 74HCT40103DB |
| 厂家： | 
NXP |
| 描述： | 8-bit synchronous binary down counter |
| 文件： | 总17页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT40103
8-bit synchronous binary down
counter
1998 Jul 08
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Counting is inhibited when the terminal enable input (TE)
is HIGH. The terminal count output (TC) goes LOW when
the count reaches zero if TE is LOW, and remains LOW for
one full clock period.
FEATURES
• Cascadable
• Synchronous or asynchronous preset
• Output capability: standard
• ICC category: MSI
When the synchronous preset enable input (PE) is LOW,
data at the jam input (P0 to P7) is clocked into the counter
on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input
(PL) is LOW, data at the jam input (P0 to P7) is
GENERAL DESCRIPTION
The 74HC/HCT40103 are high-speed Si-gate CMOS
devices and are pin compatible with the “40103” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
asynchronously forced into the counter regardless of the
state of PE, TE, or CP. The jam inputs (P0 to P7) represent
a single 8-bit binary word.
When the master reset input (MR) is LOW, the counter is
asynchronously cleared to its maximum count (decimal
255) regardless of the state of any other input. The
precedence relationship between control inputs is
indicated in the function table.
The 74HC/HCT40103 consist each of an 8-bit
synchronous down counter with a single output which is
active when the internal count is zero. The “40103”
contains a single 8-bit binary counter and has control
inputs for enabling or disabling the clock (CP), for clearing
the counter to its maximum count, and for presetting the
counter either synchronously or asynchronously. All
control inputs and the terminal count output (TC) are
active-LOW logic.
If all control inputs except TE are HIGH at the time of zero
count, the counters will jump to the maximum count, giving
a counting sequence of 256 clock pulses long.
The “40103” may be cascaded using the TE input and the
TC output, in either a synchronous or ripple mode.
In normal operation, the counter is decremented by one
count on each positive-going transition of the clock (CP).
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH propagation delay CP to TC
CL = 15 pF; VCC = 5 V
30
32
30
31
ns
fmax
CI
maximum clock frequency
input capacitance
MHz
pF
3.5
24
3.5
27
CPD
power dissipation capacitance per package notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
1998 Jul 08
2
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC40103N;
74HCT40103N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HC40103D;
74HCT40103D
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC40103DB;
74HCT40103DB
SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
SOT403-1
74HC40103PW; TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
CP
clock input (LOW-to-HIGH, edge-triggered)
asynchronous master reset input (active LOW)
terminal enable input
2
MR
3
TE
4, 5, 6, 7, 10, 11, 12, 13
P0 to P7
GND
PL
jam inputs
8
ground (0 V)
9
asynchronous preset enable input (active LOW)
terminal count output (active LOW)
synchronous preset enable input (active LOW)
positive supply voltage
14
15
16
TC
PE
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
3
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Fig.4 Functional diagram.
FUNCTION TABLE
CONTROL INPUTS
PRESET MODE ACTION
MR
PL
PE
TE
H
H
H
H
L
H
H
H
L
H
H
L
H
L
inhibit counter
count down
synchronous
asynchronous
X
X
X
preset on next LOW-to HIGH clock transition
preset asynchronously
X
X
X
clear to maximum count
Note
1. Clock connected to CP.
Synchronous operation: changes occur on the LOW-to-HIGH CP transition.
Jam inputs: MSD = P7, LSD = P0.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
APPLICATIONS
• Divide-by-n counters
• Programmable timers
• Interrupt timers
• Cycle/program counters
1998 Jul 08
4
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Fig.5 Logic diagram.
Fig.6 Timing diagram.
1998 Jul 08
5
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
ns
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to TC
96
35
28
50
18
14
300
60
375
75
450
90
2.0 Fig.7
4.5
51
64
77
6.0
tPHL/ tPLH propagation delay
TE to TC
175
35
220
44
265
53
ns
2.0 Fig.8
4.5
30
37
45
6.0
t
PHL/ tPLH propagation delay
PL to TC
102 315
395
79
475
95
ns
2.0 Fig.9
37
63
53
275
55
47
75
15
13
4.5
30
40
81
6.0
tPHL
propagation delay
MR to TC
83
345
69
415
83
ns
2.0 Fig.9
30
4.5
24
59
71
6.0
tTHL/ tTLH output transition time
19
95
110
22
ns
2.0 Figs 7 and 8
7
6
19
4.5
16
19
6.0
tW
tW
tW
trem
tsu
clock pulse width
HIGH or LOW
165 22
205
41
35
155
31
26
155
31
26
65
13
11
250
50
ns
2.0 Fig.7
33
28
8
6
4.5
43
6.0
master reset pulse width
LOW
125 39
190
38
ns
2.0 Fig.9
25
21
14
11
4.5
32
6.0
preset enable pulse width 125 33
PL; LOW
190
38
ns
2.0 Fig.9
25
21
50
10
9
12
10
14
5
4.5
32
6.0
removal time
75
ns
2.0 Fig.10
MR to CP or PL to CP
15
4.5
4
13
6.0
set-up time
PE to CP
75
15
13
22
8
95
19
16
110
22
ns
2.0 Fig.11
4.5
6.0
6
19
1998 Jul 08
6
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
ns
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tsu
tsu
th
set-up time
TE to CP
150 44
190
38
33
95
19
16
0
225
45
38
110
22
19
0
2.0 Fig.11
30
26
75
15
13
0
16
13
22
8
4.5
6.0
set-up time
Pn to CP
ns
2.0 Fig.12
4.5
6
6.0
hold time
PE to CP
−14
−5
−4
−30
−11
−9
−17
−6
−5
ns
2.0 Fig.11
0
0
0
4.5
0
0
0
6.0
th
hold time
TE to CP
0
0
0
ns
2.0 Fig.11
0
0
0
4.5
0
0
0
6.0
th
hold time
Pn to CP
0
0
0
ns
2.0 Fig.12
0
0
0
4.5
6.0
0
0
0
fmax
maximum clock pulse
frequency
3.0 10
2.4
12
14
2.0
10
12
MHz 2.0 Fig.7
15
18
29
35
4.5
6.0
1998 Jul 08
7
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
CP, PE
MR
TE
1.50
1.00
0.80
0.35
0.25
PL
Pn
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to TC
35
23
44
29
7
60
40
75
55
15
75
50
94
69
19
90
60
112
83
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.8
4.5 Fig.9
4.5 Fig.9
4.5 Figs. 7 and 8
4.5 Fig.7
4.5 Fig.9
4.5 Fig.9
4.5 Fig.10
4.5 Fig.11
4.5 Fig.11
tPHL/ tPLH propagation delay
TE to TC
tPHL/ tPLH propagation delay
PL to TC
tPHL
propagation delay
MR to TC
tTHL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
33
30
10
16
22
1
41
38
48
13
25
50
50
45
57
15
30
60
tW
master reset pulse width
LOW
tW
preset enable pulse width 38
PL; LOW
trem
tsu
tsu
removal time
10
20
40
MR to CP or PL to CP
set-up time
PE to CP
11
20
set-up time
TE to CP
1998 Jul 08
8
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tsu
th
set-up time
Pn to CP
20
11
25
30
ns
ns
ns
ns
4.5 Fig.12
4.5 Fig.11
4.5 Fig.11
4.5 Fig.12
hold time
PE to CP
2
−3
−10
−5
28
2
2
th
hold time
TE to CP
0
0
0
th
hold time
Pn to CP
0
0
0
fmax
maximum clock pulse
frequency
15
12
10
MHz 4.5 Fig.7
1998 Jul 08
9
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock input (CP) to
TC propagation delays, the clock pulse width,
the output transition times and the maximum
clock pulse frequency.
Fig.8 Waveforms showing the TE to TC
propagation delays.
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing PL, MR, Pn to TC
propagation delays.
Fig.10 Waveforms showing removal time for
MR and PL.
The shaded areas indicate when the input is permitted to change
for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing hold and set-up times for
MR or PE to CP.
Fig.12 Waveforms showing hold and set-up times
for Pn, PE to CP.
1998 Jul 08
10
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
APPLICATION INFORMATION
Fig.13 Programmable timer.
V
CC
f
IN
1
P
=
TC
TE
PE
f
OUT
0
N
N
40103
GND
PL
MR
CP
f
P
IN
7
MGA836
Fig.14 Divide-by-N counter.
1998 Jul 08
11
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
max.
min.
max.
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
3.9
3.4
8.25
7.80
9.5
8.3
4.7
0.51
3.7
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.021
0.015
0.013
0.009
0.86
0.84
0.32
0.31
0.055
0.045
0.26
0.24
0.15
0.13
0.37
0.33
inches
0.19
0.020
0.15
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-10-02
95-01-19
SOT38-1
050G09
MO-001AE
1998 Jul 08
12
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1998 Jul 08
13
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2.0
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-01-14
95-02-04
SOT338-1
MO-150AC
1998 Jul 08
14
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-07-12
95-04-04
SOT403-1
MO-153
1998 Jul 08
15
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
DIP
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Even with these conditions:
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
REPAIRING SOLDERED JOINTS
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
SO, SSOP and TSSOP
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1998 Jul 08
16
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less
than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a
dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jul 08
17
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