74HCT4060PW [NXP]
14-stage binary ripple counter with oscillator; 与振荡器的14级二进制纹波计数器
| 型号： | 74HCT4060PW |
| 厂家： | 
NXP |
| 描述： | 14-stage binary ripple counter with oscillator |
| 文件： | 总12页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4060
14-stage binary ripple counter with
oscillator
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
terminals (RS, RTC and CTC), ten buffered outputs (Q3 to
Q9 and Q11 to Q13) and an overriding asynchronous
master reset (MR).
The oscillator configuration allows design of either RC or
crystal oscillator circuits. The oscillator may be replaced by
an external clock signal at input RS. In this case keep the
other oscillator pins (RTC and CTC) floating.
FEATURES
• All active components on chip
• RC or crystal oscillator configuration
• Output capability: standard (except for RTC and CTC
• ICC category: MSI
)
The counter advances on the negative-going transition of
RS. A HIGH level on MR resets the counter (Q3 to Q9 and
Q11 to Q13 = LOW), independent of other input conditions.
GENERAL DESCRIPTION
The 74HC/HCT4060 are high-speed Si-gate CMOS
devices and are pin compatible with “4060” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
In the HCT version, the MR input is TTL compatible, but
the RS input has CMOS input switching levels and can be
driven by a TTL output by using a pull-up resistor to VCC
.
The 74HC/HCT4060 are 14-stage ripple-carry
counter/dividers and oscillators with three oscillator
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH propagation delay
RS to Q3
CL = 15 pF; VCC = 5 V
31
6
31
6
ns
Qn to Qn+1
ns
tPHL
fmax
CI
MR to Qn
17
87
3.5
40
18
88
3.5
40
ns
maximum clock frequency
input capacitance
MHz
pF
pF
CPD
power dissipation capacitance per package
notes 1, 2 and 3
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
3. For formula on dynamic power dissipation see next pages.
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
PIN DESCRIPTION
PIN NO.
SYMBOL
11 to Q13
NAME AND FUNCTION
1, 2, 3
Q
counter outputs
7, 5, 4, 6, 14, 13, 15
Q3 to Q9
GND
CTC
counter outputs
8
ground (0 V)
9
external capacitor connection
external resistor connection
clock input/oscillator pin
master reset
10
11
12
16
RTC
RS
MR
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
DYNAMIC POWER DISSIPATION FOR 74HC
PARAMETER
VCC (V) TYPICAL FORMULA FOR PD (µW) (note 1)
total dynamic power
dissipation when using the
on-chip oscillator (PD)
2.0
4.5
6.0
C
C
C
PD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc
+
60 × VCC
PD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 1 750 × VCC
PD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 3 800 × VCC
Note
1. GND = 0 V; Tamb = 25 °C
DYNAMIC POWER DISSIPATION FOR 74HCT
PARAMETER
VCC (V) TYPICAL FORMULA FOR PD (µW) (note 1)
4.5
PD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 1 750 × VCC
total dynamic power
dissipation when using the
on-chip oscillator (PD)
C
Notes
1. GND = 0 V; Tamb = 25 °C
2. Where: fo = output frequency in MHz
fosc = oscillator frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
Ct = timing capacitance in pF
VCC = supply voltage in V
Fig.4 Functional diagram.
APPLICATIONS
• Control counters
• Timers
• Frequency dividers
• Time-delay circuits
December 1990
4
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
Fig.5 Logic diagram.
Fig.6 Timing diagram.
December 1990
5
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
DC CHARACTERISTICS FOR 74HC
Output capability: standard (except for RTC and CTC
)
I
CC category: MSI
Voltages are referenced to GND (ground = 0 V)
T
amb (°C)
74HC
TEST CONDITIONS
SYM-
BOL
PARAMETER
UNIT
VI
OTHER
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
VIH
VIL
HIGH level input voltage
MR input
1.5
3.15 2.4
4.2
1.3
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
V
V
V
V
V
2.0
4.5
6.0
3.1
LOW level input voltage
MR input
0.8 0.5
2.1 1.35
2.8 1.8
0.5
1.35
1.8
0.5
1.35
1.8
2.0
4.5
6.0
VIH
VIL
HIGH level input voltage
RS input
1.7
3.6
4.8
1.7
3.6
4.8
1.7
3.6
4.8
2.0
4.5
6.0
LOW level input voltage
RS input
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
2.0
4.5
6.0
VOH
HIGH level output voltage 3.98
3.84
5.34
3.7
5.2
4.5 RS=GND −IO = 2.6 mA
6.0 and −IO = 3.3 mA
MR=GND
4.5 RS=VCC −IO = 0.65 mA
6.0 and −IO = 0.85 mA
MR=VCC
2.0 RS=GND −IO = 20 µA
4.5 and −IO = 20 µA
R
TC output
5.48
3.98
5.48
3.84
5.34
3.7
5.2
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
6.0 MR=GND −IO = 20 µA
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
2.0 RS=VCC −IO = 20 µA
4.5 and
6.0 MR=VCC −IO = 20 µA
−IO = 20 µA
VOH
VOH
VOH
VOL
HIGH level output voltage 3.98
TC output 5.48
3.84
5.34
3.7
5.2
4.5 RS=VIH
6.0 and
MR=VIL
−IO = 3.2 mA
−IO = 4.2 mA
C
HIGH level output voltage 1.9
except RTC output
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
2.0 VIH
4.5 or
6.0 VIL
−IO = 20 µA
−IO = 20 µA
−IO = 20 µA
4.4
5.9
HIGH level output voltage 3.98
except RTC and CTC
outputs
3.84
5.34
3.7
5.2
4.5 VIH
6.0 or
VIL
−IO = 4.0 mA
−IO = 5.2 mA
5.48
LOW level output voltage
0.26
0.26
0.33
0.33
0.4
0.4
4.5 RS=VCC
6.0 and
I
I
O = 2.6 mA
O = 3.3 mA
R
TC output
MR=GND
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
2.0 RS=VCC
4.5 and
6.0 MR=GND
I
I
I
O = 20 µA
O = 20 µA
O = 20 µA
December 1990
6
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
T
amb (°C)
74HC
TEST CONDITIONS
SYM-
BOL
PARAMETER
UNIT
VI
OTHER
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
VOL
VOL
VOL
±II
LOW level output voltage
0.26
0.26
0.33
0.33
0.4
0.4
V
4.5 RS=VIL
6.0 and
MR=VIH
IO = 3.2 mA
C
TC output
I
O = 4.2 mA
LOW level output voltage
except RTC output
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
2.0 VIH
4.5 or
6.0 VIL
IO = 20 µA
I
I
O = 20 µA
O = 20 µA
LOW level output voltage
except RTC and CTC
outputs
0.26
0.26
0.33
0.33
0.4
0.4
V
4.5 VIH
6.0 or
VIL
IO = 4.0 mA
O = 5.2 mA
I
input leakage current
0.1
8.0
1.0
1.0
µA
6.0 VCC
or
GND
ICC
quiescent supply current
80.0
160.0 µA
6.0 VCC
or
IO = 0
GND
December 1990
7
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
99
36
29
300
60
51
375
75
64
450
90
77
2.0
4.5 Fig.12
6.0
propagation delay
RS to Q3
t
t
PHL/ tPLH
ns
ns
ns
ns
ns
ns
ns
22
8
6
80
16
14
100
20
17
120
24
20
2.0
4.5 Fig.14
6.0
propagation delay
Qn to Qn+1
PHL/ tPLH
55
20
16
175
35
30
220
44
37
265
53
45
2.0
4.5 Fig.13
6.0
propagation delay
MR to Qn
tPHL
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5 Fig.12
6.0
t
THL/ tTLH output transition time
clock pulse width
80 17
100
20
17
120
24
20
2.0
4.5 Fig.12
6.0
tW
16
14
6
5
RS; HIGH or LOW
80 25
100
20
17
120
24
20
2.0
4.5 Fig.13
6.0
master reset pulse
width MR; HIGH
tW
16
14
9
7
100 28
20 10
125
25
21
150
30
26
2.0
4.5 Fig.13
6.0
removal time
MR to RS
trem
17
8
6.0 26
30 80
35 95
4.8
24
28
4.0
20
24
2.0
maximum clock pulse
frequency
fmax
MHz 4.5 Fig.12
6.0
December 1990
8
DC CHARACTERISTICS FOR 74HCT
Output capability: standard (except for RTC and CTC
)
I
CC category: MSI
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
UNIT
SYMBOL PARAMETER
VI
OTHER
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
VIH
VIL
HIGH level input voltage
LOW level input voltage
HIGH level output voltage
2.0
2.0
2.0
V
V
V
V
V
V
V
4.5 to 5.5
4.5 to 5.5
4.5
note 2
note 2
0.8
0.8
0.8
VOH
3.98
3.84
3.84
4.4
3.7
3.7
4.4
4.4
3.7
RS=GND and MR=GND −IO = 2.6 mA
RS = VCC and MR = VCC −IO = 0.65 mA
RS=GND and MR=GND −IO = 20 µA
RTC output
3.98
4.5
4.4 4.5
4.4 4.5
3.98
4.5
4.4
4.5
RS=VCC and MR=VCC
RS = VIH and MR = VIL
−IO = 20 µA
VOH
VOH
VOH
HIGH level output voltage
TC output
3.84
4.5
−IO = 3.2 mA
C
HIGH level output voltage
except RTC output
4.4 4.5
3.98
4.4
4.4
3.7
V
V
4.5
4.5
VIH or VIL
VIH or VIL
−IO = 20 µA
HIGH level output voltage
except RTC and CTC
outputs
3.84
−IO = 4.0 mA
VOL
LOW level output voltage
0.26
0.1
0.33
0.1
0.4
0.1
0.4
V
V
V
4.5
4.5
4.5
RS=VCC and MR=GND
RS=VCC and MR=GND
RS = VIL and MR = VIH
IO = 2.6 mA
IO = 20 µA
IO = 3.2 mA
R
TC output
LOW level output voltage
TC output
0
0
VOL
VOL
VOL
0.26
0.33
C
LOW level output voltage
except RTC output
0.1
0.1
0.1
0.4
V
V
4.5
4.5
VIH or VIL
VIH or VIL
IO = 20 µA
LOW level output voltage
except RTC and CTC
outputs
0.26
0.33
IO = 4.0 mA
±I
input leakage current
0.1
8.0
1.0
1.0
µA
5.5
VCC or GND
VCC or GND
ICC
∆ICC
quiescent supply current
80.0
450
160.0 µA
490 µA
5.5
IO = 0
additional quiescent supply
current per input pin for unit
load coefficient is 1 (note 1)
100 360
4.5 to 5.5
VCC − 2.1 V
other inputs at
VCC or GND;
I
O = 0
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
Notes
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
2. Only input MR (pin 12) has TTL input switching levels for the HCT versions.
INPUT
UNIT LOAD COEFFICIENT
MR
0.40
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
RS to Q3
33
8
66
16
44
15
83
20
55
19
99
24
66
22
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.12
4.5 Fig.14
4.5 Fig.13
4.5 Fig.12
4.5 Fig.12
4.5 Fig.13
4.5 Fig.13
t
PHL/ tPLH propagation delay
Qn to Qn+1
tPHL
propagation delay
MR to Qn
21
7
t
THL/ tTLH output transition time
tW
clock pulse width
RS; HIGH or LOW
16
16
26
30
6
20
20
33
24
24
24
39
20
tW
master reset pulse
width MR; HIGH
6
trem
fmax
removal time
MR to RS
13
80
maximum clock pulse
frequency
MHz 4.5 Fig.12
December 1990
10
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
MBA333
14
handbook, halfpage
g
max.
fs
(mA/V)
12
typ.
10
8
min.
6
4
Fig.7 Test set-up for measuring forward
transconductance gfs = dio / dvi at vo is
constant (see also graph Fig.8);
MR = LOW.
2
0
1
2
3
4
5
6
V
(V)
CC
Fig.8 Typical forward transconductance gfs as a
function of the supply voltage VCC at
Tamb = 25 °C.
RC OSCILLATOR
Typical formula for oscillator frequency:
1
fosc
=
-------------------------------
2.5 × Rt × Ct
Fig.9 RC oscillator frequency as a function of
Rt and Ct at VCC = 2.0 to 6.0 V; Tamb = 25 °C.
Ct curve at Rt = 100 kΩ; R2 = 200 kΩ.
Rt curve at Ct = 1 nF; R2 = 2 × Rt.
Fig.10 Example of a RC oscillator.
TIMING COMPONENT LIMITATIONS
The oscillator frequency is mainly determined by RtCt, provided R2 ≈ 2Rt and R2C2 << RtCt. The function of R2 is to
minimize the influence of the forward voltage across the input protection diodes on the frequency. The stray capacitance
C2 should be kept as small as possible. In consideration of accuracy, Ct must be larger than the inherent stray
capacitance. Rt must be larger than the “ON” resistance in series with it, which typically is 280 Ω at VCC = 2.0 V, 130 Ω at
VCC = 4.5 V and 100 Ω at VCC = 6.0 V.
The recommended values for these components to maintain agreement with the typical oscillation formula are:
Ct > 50 pF, up to any practical value,
10 kΩ < Rt < 1 MΩ.
In order to avoid start-up problems, Rt ≥ 1 kΩ.
December 1990
11
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
74HC/HCT4060
TYPICAL CRYSTAL OSCILLATOR
In Fig.11, R2 is the power limiting resistor.
For starting and maintaining oscillation a minimum
transconductance is necessary, so R2 should not
be too large. A practical value for R2 is 2.2 kΩ.
Fig.11 External components connection for a crystal oscillator.
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing the master reset (MR)
pulse width, the master reset to output (Qn)
propagation delays and the master reset to
clock (RS) removal time.
Fig.12 Waveforms showing the clock (RS) to
output (Q3) propagation delays, the clock
pulse width, the output transition times and
the maximum clock frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing the output (Qn) to Qn+1 propagation delays.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
12
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