74HCT4516DB [NXP]
Binary up/down counter; 二进制加/减计数器
| 型号： | 74HCT4516DB |
| 厂家： | 
NXP |
| 描述： | Binary up/down counter |
| 文件： | 总14页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4516
Binary up/down counter
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
parallel load input (PL), four parallel inputs (D0 to D3), four
parallel outputs (Q0 to Q3), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).
FEATURES
• Output capability: standard
• ICC category: MSI
Information on D0 to D3 is loaded into the counter while PL
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. When PL and CE are
LOW, the counter changes on the LOW-to-HIGH transition
of CP. UP/DN determines the direction of the count, HIGH
for counting up, LOW for counting down. When counting
up, TC is LOW when Q0 to Q3 are HIGH and CE is LOW.
When counting down, TC is LOW when Q0 to Q3 and CE
are LOW. A HIGH on MR resets the counter (Q0 to
GENERAL DESCRIPTION
The 74HC/HCT4516 are high-speed Si-gate CMOS
devices and are pin compatible with the “4516” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4516 are edge-triggered synchronous
up/down 4-bit binary counters with a clock input (CP), an
up/down count control input (UP/DN), an active LOW
count enable input (CE), an asynchronous active HIGH
Q3 = LOW) independent of all other input conditions.
Logic equation for terminal count:
TC = CE . {(UP/DN) . Q0 . Q1 . Q2 . Q3 + (UP ⁄ DN) . Q0 . Q1 . Q2 . Q3}
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
HC HCT
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
t
PHL/ tPLH
propagation delay CP to Qn
maximum clock frequency
input capacitance
19
45
3.5
59
19
57
3.5
61
CL = 15 pF; VCC = 5 V
fmax
CI
MHz
pF
CPD
power dissipation capacitance per package
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
PIN DESCRIPTION
PIN NO.
SYMBOL
PL
NAME AND FUNCTION
1
parallel load input (active HIGH)
parallel inputs
4, 12, 13, 3
D0 to D3
CE
5
count enable input (active LOW)
parallel outputs
6, 11, 14, 2
Q0 to Q3
TC
7
terminal count output (active LOW)
ground (0 V)
8
GND
MR
9
asynchronous master reset input (active HIGH)
up/down control input
10
15
16
UP/DN
CP
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
VCC
Fig.2
Fig.3 IEC logic symbol.
Fig.1 Pin configuration.
December 1990
3
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
FUNCTION TABLE
MR PL UP/DN
CE
CP
MODE
L
L
L
L
H
X
X
L
H
X
X
H
L
L
X
X
X
↑
↑
X
parallel load
no change
count down
count up
L
L
L
X
H
reset
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition
Fig.4 Functional diagram.
Fig.5 Timing diagram.
December 1990
4
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
Fig.6 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to+85
−40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
72
26
21
220
44
37
275
55
47
330
66
56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
Fig.7
tPHL
propagation delay
MR to Qn
69
25
20
210
42
36
265
53
45
315
63
54
2.0
4.5
6.0
Fig.10
Fig.9
t
t
t
PLH/ tPHL propagation delay
83
30
24
250
50
43
315
63
54
375
75
64
2.0
4.5
6.0
PL to Qn
PHL/ tPLH propagation delay
CP to TC
74
27
22
260
52
44
325
65
55
395
78
66
2.0
4.5
6.0
Fig.7
PHL/ tPLH propagation delay
CE to TC
36
13
10
125
25
21
155
31
26
190
38
32
2.0
4.5
6.0
Fig.8
tPLH
propagation delay
MR to TC
69
25
20
235
47
40
295
59
50
355
71
60
2.0
4.5
6.0
Fig.10
Fig.9
t
t
PLH/ tPHL propagation delay
91
33
26
300
60
51
375
75
64
450
90
77
2.0
4.5
6.0
PL to TC
TLH/ tTHL output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
Fig.9
tW
tW
tW
clock pulse width CP, 80
CE HIGH or LOW
25
9
7
100
20
17
120
24
20
2.0
4.5
6.0
Fig.7
16
14
parallel load pulse
width HIGH
80
16
14
28
10
8
100
20
17
120
24
20
2.0
4.5
6.0
Fig.10
Fig.10
master reset pulse
width HIGH
80
16
14
19
7
6
100
20
17
120
24
20
2.0
4.5
6.0
December 1990
6
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
T
amb (°C)
74HC
TEST CONDITIONS
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to+85
−40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
trem
trem
tsu
tsu
tsu
th
removal time
MR to CP
80
16
14
28
10
8
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.10
removal time
PL to CP
80
16
14
25
9
7
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.10
Fig.8
Fig.8
Fig.11
Fig.8
Fig.11
Fig.8
Fig.7
set-up time
UP/DN to CP
100 30
20
17
125
25
21
150
30
26
ns
2.0
4.5
6.0
11
9
set-up time
CE to CP
100 19
20
17
125
25
21
150
30
26
ns
2.0
4.5
6.0
7
6
set-up time
Dn to PL
100 17
20
17
125
25
21
150
30
26
ns
2.0
4.5
6.0
6
5
hold time
CE to CP
5
5
5
0
0
0
5
5
5
5
5
5
ns
2.0
4.5
6.0
th
hold time
Dn to PL
3
3
3
−6
−2
−2
3
3
3
3
3
3
ns
2.0
4.5
6.0
th
hold time
UP/DN to CP
0
0
0
−19
−7
−6
0
0
0
0
0
0
ns
2.0
4.5
6.0
fmax
maximum clock pulse 6.0
frequency
16
49
58
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
30
35
December 1990
7
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Dn
0.75
1.00
1.00
1.25
1.50
PL, CE
UP/DN
CP
MR
December 1990
8
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
74HCT
TEST CONDITIONS
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85
−40 to+125
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH
tPHL
PLH/ tPHL
tPHL/ tPLH
PHL/ tPLH
tPLH
propagation delay
CP to Qn
28
24
32
29
18
31
34
7
50
42
53
58
31
50
68
15
63
53
66
73
39
63
85
19
75
63
80
87
47
75
102
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Fig.7
propagation delay
MR to Qn
Fig.10
Fig.9
t
propagation delay
PL to Qn
propagation delay
CP to TC
Fig.7
t
propagation delay
CE to TC
Fig.8
propagation delay
MR to TC
Fig.10
Fig.9
t
PLH/ tPHL
TLH/ tTHL
propagation delay
PL to TC
t
output transition time
Fig.9
tW
clock pulse width CP, 16
CE HIGH or LOW
9
20
20
25
29
21
25
25
25
13
24
24
30
35
26
30
30
30
15
Fig.7
tW
parallel load pulse
width HIGH
16
20
23
17
20
20
20
10
8
Fig.10
Fig.10
Fig.10
Fig.10
Fig.8
tW
master rest pulse
width HIGH
5
trem
trem
tsu
tsu
tsu
th
removal time
MR to CP
14
10
11
9
removal time
PL to CP
set-up time
UP/DN to CP
set-up time
CE to CP
Fig.8
set-up time
Dn to PL
9
Fig.11
Fig.8
hold time
CE to CP
9
December 1990
9
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
T
amb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85
−40 to+125
WAVEFORMS
min. typ. max. min. max. min. max.
th
hold time
Dn to PL
5
−6
−5
52
5
5
ns
ns
4.5
4.5
Fig.11
Fig.8
Fig.7
th
hold time
UP/DN to CP
0
0
0
fmax
maximum clock pulse 30
frequency
24
20
MHz 4.5
December 1990
10
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the set-up and hold
times form count enable (CE) and up/down
(UP/DN) control inputs to the clock pulse
(CP), the propagation delays from UP/DN,
CE to TC.
Fig.7 Waveforms showing the clock (CP) to
output (Qn) and terminal count (TC)
propagation delays, the clock pulse width
and the maximum clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the preset enable
pulse width, preset enable to output
delays and output transition times.
Fig.10 Waveforms showing the master reset pulse,
master reset to terminal count and Qn
delay and master reset to clock removal
time.
December 1990
11
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the data set-up and hold times to parallel load (PL).
December 1990
12
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
APPLICATION INFORMATION
Terminal count (TC) lines at the 2nd, 3rd, etc. Stages may have a negative-going glitch pulse resulting from differential
delays of different 4516s. These negative-going glitches do not affect proper 4516 operation. However, if the terminal
count signals are used to trigger other edge-sensitive logic devices, such as flip-flops or counters, the terminal count
signals should be gated with the clock signal using a 2-input OR gate such as HC/HCT32.
Fig.12 Cascading counter packages (parallel clocking).
Ripple clocking mode: the UP/DN control can be changed at any count. The only restriction on changing the
UP/DN control is that the clock input to the first counting stage must be “HIGH”. For cascading counters operating in a
fixed up-count or down-count mode, the OR gates are not required between stages and TC is connected directly to the
CP input of the next stage with CE grounded.
Fig.13 Cascading counter packages (ripple clocking).
December 1990
13
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
Use the following formulae to calculate
Ntotal
:
i
Ntotal
=
(16 × N ) + N0
i
π
1
f
out = fin/Ntotal
Fig.15 Programmable cascaded frequency divider.
Fig.14 State diagram.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
parallel inputs
count-up count-down
n
n
D3
D2
D1
D0
(1)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Note
1. no count; fout is HIGH.
December 1990
14
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