74HCT4518DB [NXP]
IC HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, Counter;
| 型号： | 74HCT4518DB |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, Counter 计数器 CD |
| 文件： | 总7页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4518
Dual synchronous BCD counter
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Dual synchronous BCD counter
74HC/HCT4518
all four bit positions (nQ0 to nQ3) and an active HIGH
overriding asynchronous master reset input (nMR).
FEATURES
• Output capability: standard
• ICC category: MSI
The counter advances on either the LOW-to-HIGH
transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW
transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1
may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ0 to nQ3 = LOW)
independent of nCP0 and nCP1.
GENERAL DESCRIPTION
The 74HC/HCT4518 are high-speed Si-gate CMOS
devices and are pin compatible with the “4518” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
APPLICATIONS
The 74HC/HCT4518 are dual 4-bit internally synchronous
BCD counters with an active HIGH clock input (nCP0) and
an active LOW clock input (nCP1), buffered outputs from
• Multistage synchronous counting
• Multistage asynchronous counting
• Frequency dividers
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH propagation delay nCP0, nCP1 to nQn
CL = 15 pF; VCC = 5 V 20
24
14
55
3.5
27
ns
ns
tPHL
fmax
CI
propagation delay nMR to nQn
maximum clock frequency
input capacitance
13
61
3.5
MHz
pF
CPD
power dissipation capacitance per counter notes 1 and 2
29
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Dual synchronous BCD counter
74HC/HCT4518
PIN DESCRIPTION
PIN NO.
1, 9
SYMBOL
1CP0, 2CP0
1CP1, 2CP1
1Q0 to 1Q3
1MR, 2MR
GND
NAME AND FUNCTION
clock inputs (LOW-to-HIGH, edge-triggered)
clock inputs (HIGH-to-LOW, edge-triggered)
data outputs
2, 10
3, 4, 5, 6
7, 15
asynchronous master reset inputs (active HIGH)
ground (0 V)
8
11, 12, 13, 14
16
2Q0 to 2Q3
VCC
data outputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual synchronous BCD counter
74HC/HCT4518
FUNCTION TABLE
nCP0
nCP1
MR
L
MODE
↑
H
↓
counter advances
counter advances
no change
L
↓
L
X
↑
L
X
↑
L
no change
L
↓
L
no change
H
X
L
no change
X
H
Q0 to Q3 = LOW
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition
↓ = HIGH-to-LOW clock transition
Fig.4 Functional diagram.
Fig.5 Logic diagram (one counter).
Fig.6 Timing diagram.
December 1990
4
Philips Semiconductors
Product specification
Dual synchronous BCD counter
74HC/HCT4518
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP0, nCP1 to nQn
66
24
19
210
42
36
265
53
45
315
63
59
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
Fig.9
tPHL
propagation delay
nMR to nQn
44
16
13
150
30
26
190
38
33
225
45
38
2.0
4.5
6.0
Fig.8
Fig.9
Fig.8
Fig.8
Fig.8
Fig.7
Fig.8
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
25
9
7
100
20
17
120
24
20
2.0
4.5
6.0
tW
master reset pulse width 120 39
150
30
26
180
36
31
2.0
4.5
6.0
HIGH
24
20
14
11
trem
tsu
fmax
removal time
nMR to nCP0, nCP1
0
0
0
−22
−8
−6
0
0
0
0
0
0
2.0
4.5
6.0
set-up time
nCP1 to nCP0;
nCP0 to nCP1
80
16
14
22
8
6
100
20
17
120
24
20
2.0
4.5
6.0
maximum clock pulse
frequency
6.0
30
35
18
55
66
4.8
24
28
4.0
20
24
MHz 2.0
4.5
nCP0, nCP1
6.0
December 1990
5
Philips Semiconductors
Product specification
Dual synchronous BCD counter
74HC/HCT4518
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
nCP0, nCP1
nMR
0.80
1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP0, nCP1 to nQn
28
17
7
53
35
15
66
44
19
80
53
22
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.9
4.5 Fig.8
4.5 Fig.9
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.7
tPHL
propagation delay
nMR to nQn
t
THL/ tTLH output transition time
tW
tW
trem
tsu
clock pulse width
HIGH or LOW
20
11
11
−11
5
25
25
0
30
30
0
master reset pulse width 20
HIGH
removal time
nMR to nCP0, nCP1
0
set-up time
16
20
24
nCP1 to nCP0;
nCP0 to nCP1
fmax
maximum clock pulse
frequency
25
50
20
17
MHz 4.5 Fig.8
nCP0, nCP1
December 1990
6
Philips Semiconductors
Product specification
Dual synchronous BCD counter
74HC/HCT4518
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing hold and set-up times for nCP0 to nCP1 and nCP1 to nCP0.
Conditions:
nCP1 = HIGH while nCP0 is triggered on a
LOW-to-HIGH transition and nCP0 = LOW,
while nCP1 is triggered on a HIGH-to-LOW transition.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the minimum pulse widths for nCP0, nCP1 and nMR inputs; the removal time for nMR
and the propagation delay for nMR to nQn outputs and the maximum clock pulse frequency.
Conditions:
nCP1 = HIGH while nCP0 is triggered on a
LOW-to-HIGH transition and nCP0 = LOW,
while nCP1 is triggered on a HIGH-to-LOW transition.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the propagation delays for nCP0, nCP1 to nQn outputs and the output transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
相关型号：
74HCT4520DB-T
IC HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, PLASTIC, SSOP-16, Counter
NXP
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