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74HCT4520DB,112 [NXP]

74HC(T)4520 - Dual 4-bit synchronous binary counter SSOP1 16-Pin;
74HCT4520DB,112
型号： 74HCT4520DB,112
厂家： NXP    NXP
描述：

74HC(T)4520 - Dual 4-bit synchronous binary counter SSOP1 16-Pin

输入元件 光电二极管 逻辑集成电路 触发器
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INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications  
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information  
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines  
74HC/HCT4520  
Dual 4-bit synchronous binary  
counter  
December 1990  
Product specification  
File under Integrated Circuits, IC06  
Philips Semiconductors  
Product specification  
Dual 4-bit synchronous binary counter  
74HC/HCT4520  
from all four bit positions (nQ0 to nQ3) and an active HIGH  
overriding asynchronous master reset input (nMR).  
FEATURES  
• Output capability: standard  
• ICC category: MSI  
The counter advances on either the LOW-to-HIGH  
transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW  
transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1  
may be used as the clock input to the counter and the other  
clock input may be used as a clock enable input. A HIGH  
on nMR resets the counter (nQ0 to nQ3 = LOW)  
independent of nCP0 and nCP1.  
GENERAL DESCRIPTION  
The 74HC/HCT4520 are high-speed Si-gate CMOS  
devices and are pin compatible with the “4520” of the  
“4000B” series. They are specified in compliance with  
JEDEC standard no. 7A.  
APPLICATIONS  
The 74HC/HCT4520 are dual 4-bit internally synchronous  
binary counters with an active HIGH clock input (nCP0)  
and an active LOW clock input (nCP1), buffered outputs  
• Multistage synchronous counting  
• Multistage asynchronous counting  
• Frequency dividers  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PARAMETER  
CONDITIONS  
UNIT  
ns  
HC  
HCT  
24  
tPHL/ tPLH  
tPHL  
propagation delay nCP0, nCP1 to nQn  
propagation delay nMR to nQn  
maximum clock frequency  
CL = 15 pF; VCC = 5 V 24  
13  
68  
13  
64  
3.5  
24  
ns  
fmax  
MHz  
pF  
CI  
input capacitance  
3.5  
29  
CPD  
power dissipation capacitance per counter  
notes 1 and 2  
pF  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
∑ (CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC − 1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
December 1990  
2
Philips Semiconductors  
Product specification  
Dual 4-bit synchronous binary counter  
74HC/HCT4520  
PIN DESCRIPTION  
PIN NO.  
1, 9  
SYMBOL  
1CP0, 2CP0  
1CP1, 2CP1  
1Q0 to 1Q3  
1MR, 2MR  
GND  
NAME AND FUNCTION  
clock inputs (LOW-to-HIGH, edge-triggered)  
clock inputs (HIGH-to-LOW, edge-triggered)  
data outputs  
2, 10  
3, 4, 5, 6  
7, 15  
asynchronous master reset inputs (active HIGH)  
ground (0 V)  
8
11, 12, 13, 14  
16  
2Q0 to 2Q3  
VCC  
data outputs  
positive supply voltage  
Fig.1 Pin configuration.  
Fig.2 Logic symbol.  
Fig.3 IEC logic symbol.  
December 1990  
3
Philips Semiconductors  
Product specification  
Dual 4-bit synchronous binary counter  
74HC/HCT4520  
FUNCTION TABLE  
nCP0 nCP1  
MR MODE  
L counter advances  
↑
H
L
↓
↓
L
L
L
L
L
H
counter advances  
no change  
X
↑
X
↑
no change  
L
↓
no change  
H
X
no change  
X
Q0 to Q3 = LOW  
Notes  
1. H = HIGH voltage level  
L = LOW voltage level  
X = don’t care  
↑ = LOW-to-HIGH clock transition  
↓ = HIGH-to-LOW clock transition  
Fig.4 Functional diagram.  
Fig.5 Logic diagram (one counter).  
Fig.6 Timing diagram.  
December 1990  
4
Philips Semiconductors  
Product specification  
Dual 4-bit synchronous binary counter  
74HC/HCT4520  
DC CHARACTERISTICS FOR 74HC  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: MSI  
AC CHARACTERISTICS FOR 74HC  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HC  
SYMBOL  
PARAMETER  
UNIT  
VCC  
(V)  
+25  
−40 to +85 −40 to +125  
WAVEFORMS  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
nCP0 to nQn  
77  
28  
22  
240  
48  
41  
300  
60  
51  
360  
72  
61  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2.0  
4.5  
6.0  
Fig.8  
t
PHL/ tPLH propagation delay  
nCP1 to nQn  
77  
28  
22  
240  
48  
41  
300  
60  
51  
360  
72  
61  
2.0  
4.5  
6.0  
Fig.8  
Fig.9  
Fig.8  
Fig.7  
Fig.7  
Fig.7  
Fig.8  
Fig.7  
tPHL  
propagation delay  
nMR to nQn  
44  
16  
13  
150  
30  
26  
190  
38  
33  
225  
45  
38  
2.0  
4.5  
6.0  
t
THL/ tTLH output transition time  
19  
7
6
75  
15  
13  
95  
19  
16  
110  
22  
19  
2.0  
4.5  
6.0  
tW  
clock pulse width  
HIGH or LOW  
80  
16  
14  
22  
8
6
100  
20  
17  
120  
24  
20  
2.0  
4.5  
6.0  
tW  
master reset pulse width 120 39  
150  
30  
26  
180  
36  
31  
2.0  
4.5  
6.0  
HIGH  
24  
20  
14  
11  
trem  
tsu  
fmax  
removal time  
nMR to nCP0; nCP1  
0
0
0
−28  
−10  
−8  
0
0
0
0
0
0
2.0  
4.5  
6.0  
set-up time  
nCP1 to nCP0;  
nCP0 to nCP1  
80  
16  
14  
14  
5
4
100  
20  
17  
120  
24  
20  
2.0  
4.5  
6.0  
maximum clock pulse  
frequency  
6.0  
30  
35  
19  
58  
69  
4.8  
24  
28  
4.0  
20  
24  
MHz 2.0  
4.5  
6.0  
December 1990  
5
Philips Semiconductors  
Product specification  
Dual 4-bit synchronous binary counter  
74HC/HCT4520  
DC CHARACTERISTICS FOR 74HCT  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: MSI  
Note to HCT types  
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.  
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.  
INPUT  
UNIT LOAD COEFFICIENT  
nCP0, nCP1  
nMR  
0.80  
1.50  
AC CHARACTERISTICS FOR 74HCT  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HCT  
SYMBOL  
PARAMETER  
UNIT  
VCC  
+25  
−40 to +85 −40 to +125  
WAVEFORMS  
(V)  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
nCP0 to nQn  
28  
25  
16  
7
53  
53  
35  
15  
66  
66  
44  
19  
80  
80  
53  
22  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4.5 Fig.8  
4.5 Fig.8  
4.5 Fig.9  
4.5 Fig.8  
4.5 Fig.7  
4.5 Fig.7  
4.5 Fig.7  
4.5 Fig.8  
t
PHL/ tPLH propagation delay  
nCP1 to nQn  
tPHL  
propagation delay  
nMR to nQn  
t
THL/ tTLH output transition time  
tW  
tW  
trem  
tsu  
clock pulse width  
HIGH or LOW  
20  
10  
12  
−8  
6
25  
25  
0
30  
30  
0
master reset pulse width 20  
HIGH  
removal time  
nMR to nCP0; nCP1  
0
set-up time  
16  
20  
24  
nCP1 to nCP0;  
nCP0 to nCP1  
fmax  
maximum clock pulse  
frequency  
30  
58  
24  
20  
MHz 4.5 Fig.7  
December 1990  
6
Philips Semiconductors  
Product specification  
Dual 4-bit synchronous binary counter  
74HC/HCT4520  
AC WAVEFORMS  
Conditions:  
nCP1 = HIGH while nCP0 is triggered on a LOW-to-HIGH transition; tW  
and trem also apply when nCP0 = LOW and nCP1 is triggered on a  
HIGH-to-LOW transition.  
(1) HC : VM = 50%; VI = GND to VCC.  
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.7 Waveforms showing removal time for nMR; minimum nCP0, nCP1, nMR pulse widths and maximum clock  
pulse frequency.  
(1) HC : VM = 50%; VI = GND to VCC.  
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.8 Waveforms showing set-up times for nCP0 to nCP1 and nCP1 to nCP0, propagation delays and output  
transition times.  
(1) HC : VM = 50%; VI = GND to VCC.  
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.9 Waveforms showing propagation delay from nMR to nQn output.  
PACKAGE OUTLINES  
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.  
December 1990  
7

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