74HCT4543DB-T [NXP]
IC HCT SERIES, SEVEN SEGMENT DECODER/DRIVER, CONFIGURABLE OUTPUT, PDSO16, Decoder/Driver;
| 型号： | 74HCT4543DB-T |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, SEVEN SEGMENT DECODER/DRIVER, CONFIGURABLE OUTPUT, PDSO16, Decoder/Driver 解码器 显示器 锁存器 驱动 CD |
| 文件： | 总11页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4543
BCD to 7-segment
latch/decoder/driver for LCDs
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
for LCDs
74HC/HCT4543
four address inputs (D0 to D3), an active HIGH latch
disable input (LD), an active HIGH blanking input (BI), an
active HIGH phase input (PH) and seven buffered
segment outputs (Qa to Qg).
FEATURES
• Latch storage of BCD inputs
• Blanking inputs
• Output capability: non-standard
• ICC category: MSI
The “4543” provides the function of a 4-bit storage latch
and an 8-4-2-1 BCD to 7-segment decoder driver. The
“4543” can invert the logic levels of the output combination.
The phase (PH), blanking (BI) and latch disable (LD)
inputs are used to reverse the function table phase, blank
the display and store a BCD code, respectively.
GENERAL DESCRIPTION
The 74HC/HCT4543 are high-speed Si-gate CMOS
devices and are pin compatible with “4543” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
For liquid crystal displays a square-wave is applied to PH
and the electrical common back-plane of the display. The
outputs of the “4543” are directly connected to the
segments of the liquid crystal.
The 74HC/HCT4543 are BCD to 7-segment
latch/decoder/drivers for liquid crystal displays. They have
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH propagation delay
CL = 15 pF; VCC = 5 V
Dn to Qn
LD to Qn
BI to Qn
29
32
20
33
ns
31
28
3.5
42
ns
ns
pF
pF
CI
input capacitance
power dissipation capacitance per package notes 1 and 2
3.5
42
CPD
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
PIN DESCRIPTION
PIN NO.
SYMBOL
LD
NAME AND FUNCTION
latch disable input (active HIGH)
address (data) inputs
phase input (active HIGH)
blanking input (active HIGH)
ground (0 V)
1
5, 3, 2, 4
D0 to D3
PH
6
7
BI
8
GND
Qa to Qg
VCC
9, 10, 11, 12, 13, 15, 14
16
segment outputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
APPLICATIONS
• Driving LCD displays
• Driving fluorescent displays
• Driving incandescent displays
• Driving gas discharge displays
Fig.4 Functional diagram.
Fig.5 Segment designation.
FUNCTION TABLE
INPUTS
PH(1)
D3
OUTPUTS
Qd
DISPLAY
LD
BI
D2
D1
D0
Qa
Qb
Qc
Qe
Qf
Qg
X
H
L
X
X
X
X
L
L
L
L
L
L
L
blank
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
L
H
L
H
H
H
L
H
L
H
L
L
L
L
L
H
H
0
1
2
3
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
L
H
L
L
H
H
H
H
L
L
L
H
L
H
H
H
L
H
H
H
L
4
5
6
7
H
H
H
H
H
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
H
L
H
H
L
H
H
L
H
H
L
H
L
L
L
H
H
L
H
H
L
8
9
blank
blank
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
blank
blank
blank
blank
(1)
H
(1)
L
L
L
X
X
X
X
as
above
as
above
H
as above
inverse of above
Notes
1. For liquid crystal displays, apply a square-wave to PH.
2. Depends upon the BCD-code previously applied when LD = HIGH.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
December 1990
4
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
Fig.6 Logic diagram.
Fig.7 Display.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
For RATINGS see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, standard outputs.
December 1990
5
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
DC CHARACTERISTICS FOR 74HC
Output capability: non-standard
ICC category: MSI
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
VI
OTHER
min. typ. max. min. max. min. max.
VIH
VIL
HIGH level input 1.5
1.2
1.5
3.15
4.2
1.5
3.15
4.2
V
2.0
4.5
6.0
voltage
3.15 2.4
4.2
3.1
LOW level input
voltage
0.7 0.5
1.8 1.35
2.8 1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
2.0
4.5
6.0
VOH
VOH
VOL
VOL
±II
HIGH level
output voltage
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
V
2.0 VIH
4.5 or
6.0 VIL
−IO = 20 µA
−IO = 20 µA
−IO = 20 µA
HIGH level
output voltage
3.98 0.15
5.48 0.16
3.84
5.34
3.7
5.2
V
4.5 VIH
6.0 or
VIL
−IO = 1.0 mA
−IO = 1.3 mA
LOW level
output voltage
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
2.0 VIH
4.5 or
6.0 VIL
IO = 20 µA
IO = 20 µA
IO = 20 µA
LOW level
output voltage
0.15 0.26
0.16 0.26
0.33
0.33
0.4
0.4
V
4.5 VIH
6.0 or
VIL
IO = 1.0 mA
IO = 1.3 mA
input leakage
current
0.1
8.0
1.0
1.0
µA
6.0 VCC
or
GND
ICC
quiescent
80.0
160.0 µA
6.0 VCC IO = 0
supply current
or
GND
December 1990
6
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
OTHER
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Dn to Qn
91
33
26
340
68
58
425
85
72
510
102
87
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.12
4.5
6.0
tPHL/ tPLH propagation delay
LD to Qn
102 370
37
30
465
93
79
555
111
94
2.0 Fig.13
4.5
6.0
74
63
t
PHL/ tPLH propagation delay
BI to Qn
66
24
19
265
53
45
330
66
56
400
80
68
2.0 Fig.14
4.5
6.0
tPHL/ tPLH propagation delay
PH to Qn
55
20
16
200
40
34
250
50
43
300
60
51
2.0
4.5
6.0
t
THL/ tTLH output transition time
63
23
18
250
50
43
315
63
54
375
75
64
2.0 Figs 12, 13 and 14
4.5
6.0
tW
tsu
th
LD pulse width
HIGH or LOW
35
7
6
11
4
3
45
9
8
55
11
9
2.0 Fig.13
4.5
6.0
set-up time
Dn to LD
60
12
10
8
3
2
75
15
13
90
18
15
2.0 Fig.15
4.5
6.0
hold time
Dn to LD
30
6
5
3
1
1
40
8
7
45
9
8
2.0 Fig.15
4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
DC CHARACTERISTICS FOR 74HCT
Output capability: non-standard
ICC category: MSI
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
VI
OTHER
min. typ. max. min. max. min. max.
VIH
VIL
HIGH level input
voltage
2.0
1.6
1.2
4.5
2.0
2.0
V
4.5
to
5.5
LOW level input
voltage
0.8
0.8
0.8
V
4.5
to
5.5
VOH
VOH
VOL
VOL
±II
HIGH level output 4.4
voltage
4.4
4.4
3.7
V
4.5 VIH
−IO = 20 µA
−IO = 1.0 mA
IO = 20 µA
or
VIL
HIGH level output 3.98 4.32
voltage
3.84
V
4.5 VIH
or
VIL
LOW level output
voltage
0
0.1
0.1
0.1
0.4
1.0
V
4.5 VIH
or
VIL
LOW level output
voltage
0.15
0.26
0.1
0.33
1.0
V
4.5 VIH
IO = 1.0 mA
or
VIL
input leakage
current
µA
5.5 VCC
or
GND
ICC
quiescent supply
current
8.0
80.0
450
160.0 µA
5.5 VCC
or
IO = 0
GND
∆ICC
additional
100
360
490
µA
4.5 VCC
other inputs
GND; IO = 0
quiescent supply
current per input
pin for unit load
coefficient is 1
(note 1)
to
−2.1V at VCC or
5.5
December 1990
8
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
D0, D1, D2
D3
BI
LD
PH
1.00
0.50
0.50
1.50
1.25
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
OTHER
74HCT
SYMBOL
PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
t
t
PHL/ tPLH propagation delay
Dn to Qn
38
36
32
24
23
4
80
68
66
66
50
100
85
83
83
63
120
102
99
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.12
4.5 Fig.13
4.5 Fig.14
4.5
PHL/ tPLH propagation delay
LD to Qn
tPHL/ tPLH propagation delay
BI to Qn
t
PHL/ tPLH propagation delay
PH to Qn
99
t
THL/ tTLH output transition time
75
4.5 Figs 12, 13 and 14
4.5 Fig.13
4.5 Fig.15
4.5 Fig.15
tW
tsu
th
LD pulse width
HIGH or LOW
10
12
8
13
15
10
15
18
12
set-up time
Dn to LD
4
hold time
Dn to LD
2
December 1990
9
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
APPLICATION DIAGRAMS
Fig.9 Connection to incandescent display
Fig.8 Connection to liquid crystal (LCD) display
readout.
readout.
Fig.10 Connection to gas discharge display
readout.
Fig.11 Connection to fluorescent display readout.
December 1990
10
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the address input (Dn)
to output (Qn) propagation delays and the
output transition times.
Fig.13 Waveforms showing the latch disable input
(LD) to output (Qn) propagation delays and
the output transition times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.15 Waveforms showing the address (Dn) to
latch disable (LD) input set-up and hold
times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
PACKAGE OUTLINES
Fig.14 Waveforms showing the blanking (BI) to
output (Qn) propagation delays and the
output transition times.
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
11
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