74HCT563DB,112 [NXP]
74HC(T)563 - Octal D-type transparent latch; 3-state; inverting SSOP2 20-Pin;型号: | 74HCT563DB,112 |
厂家: | NXP |
描述: | 74HC(T)563 - Octal D-type transparent latch; 3-state; inverting SSOP2 20-Pin 驱动 光电二极管 逻辑集成电路 |
文件: | 总7页 (文件大小:63K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT563
Octal D-type transparent latch;
3-state; inverting
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT563
TTL (LSTTL). They are specified in
common to all latches.
FEATURES
compliance with JEDEC standard no.
7A.
When LE is HIGH, data at the Dn
inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
• 3-state inverting outputs for bus
oriented applications
The 74HC/HCT563 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and inverting 3-state outputs for bus
oriented applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
• Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessor
• Common 3-state output enable
input
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
• Output capability: bus driver
• ICC category: MSI
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
The “563” is functionally identical to
the “573”, but has inverted outputs.
GENERAL DESCRIPTION
The “563” consists of eight D-type
transparent latches with 3-state
inverting outputs. The LE and OE are
The 74HC/HCT563 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
UNIT
SYMBOL
PARAMETER
CONDITIONS
HC
HCT
tPHL/ tPLH
CI
propagation delay Dn, LE to Qn
input capacitance
CL = 15 pF; VCC = 5 V
notes 1 and 2
14
3.5
19
16
3.5
19
ns
pF
pF
CPD
power dissipation capacitance per latch
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
for HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT563
PIN DESCRIPTION
PIN NO.
SYMBOL
D0 to D7
LE
NAME AND FUNCTION
2, 3, 4, 5, 6, 7, 8, 9
data inputs
11
latch enable input (active HIGH)
3-state output enable input (active LOW)
ground (0 V)
1
OE
10
GND
19, 18, 17, 16, 15, 14, 13, 12
20
Q0 to Q7
VCC
3-state latch outputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT563
FUNCTION TABLE
INPUTS
OUT-
PUTS
INTER-
NAL
OPERATING
MODES
LATCHES
Q0 to Q7
OE LE Dn
enable and
read register
L
L
H
H
L
H
L
H
H
L
latch and read
register
L
L
L
L
l
h
L
H
H
L
latch register
and disable
outputs
H
H
L
L
l
h
L
H
Z
Z
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
HIGH-to-LOW LE transition
Fig.4 Functional diagram.
Z = high impedance OFF-state
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT563
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Dn to Qn
47
17
14
145
29
25
180
36
31
220
44
38
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
t
t
t
t
PHL/ tPLH propagation delay
LE to Qn
47
17
14
145
29
25
180
36
31
220
44
38
2.0 Fig.7
4.5
6.0
PZH/ tPZL 3-state output enable
47
17
14
150
30
26
190
38
33
225
45
38
2.0 Fig.8
4.5
6.0
time
OE to Qn
PHZ/ tPLZ 3-state output disable
50
18
14
150
30
26
190
38
33
225
45
38
2.0 Fig.8
4.5
6.0
time
OE to Qn
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
2.0 Fig.6
4.5
6.0
tW
tsu
th
enable pulse width
HIGH
80
16
14
14
5
4
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
set-up time
Dn to LE
50
10
9
11
4
3
65
13
11
75
15
13
2.0 Fig.9
4.5
6.0
hold time
Dn to LE
4
4
4
−6
−2
−2
4
4
4
4
4
4
2.0 Fig.9
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT563
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Dn
LE
OE
0.35
0.65
1.25
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Dn to Qn
18
19
20
22
5
30
35
35
35
12
38
44
44
44
15
45
53
53
53
18
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.7
4.5 Fig.8
4.5 Fig.8
4.5 Fig.6
4.5 Fig.7
4.5 Fig.9
4.5 Fig.9
tPHL/ tPLH propagation delay
LE to Qn
t
PZH/ tPZL 3-state output enable
time OE to Qn
tPHZ/ tPLZ 3-state output disable
time OE to Qn
tTHL/ tTLH output transition time
tW
tsu
th
enable pulse width
HIGH
16
10
5
5
20
13
5
24
15
5
set-up time
Dn to LE
3
hold time
Dn to LE
−1
December 1990
6
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT563
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the latch enable input
(LE) pulse width, the latch enable input to
output (Qn) propagation delays and the
output transition times.
Fig.6 Waveforms showing the data input (Dn) to
output (Qn) propagation delays and the
output transition times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the data set-up and
hold times for Dn input to LE input
PACKAGE OUTLINES
(1) HC : VM = 50%; VI = GND to VCC
.
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the 3-state enable and
disable times.
December 1990
7
相关型号:
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