74HCT564NB [NXP]
IC HCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDIP20, Bus Driver/Transceiver;
| 型号： | 74HCT564NB |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDIP20, Bus Driver/Transceiver 触发器 逻辑集成电路 |
| 文件： | 总7页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT564
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
74HC/HCT564
The 74HC/HCT564 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
FEATURES
• 3-state inverting outputs for bus oriented applications
• 8-bit positive-edge triggered register
• Common 3-state output enable input
• Independent register and 3-state buffer operation
• Output capability: bus driver
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs.
• ICC category: MSI
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
GENERAL DESCRIPTION
The 74HC/HCT564 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “564” is functionally identical to the “574” but has
inverting outputs. The “564” is functionally identical to the
“534”, but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
CL = 15 pF; VCC = 5 V 15
127
HCT
tPHL/ tPLH
fmax
propagation delay CP to Qn
maximum clock frequency
input capacitance
16
62
3.5
27
ns
MHz
pF
CI
3.5
27
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi +∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
OE
3-state output enable input (active LOW)
data inputs
2, 3, 4, 5, 6, 7, 8, 9
D0 to D7
GND
CP
10
ground (0 V)
11
clock input (LOW-to-HIGH, edge-triggered)
3-state flip-flop outputs
19, 18, 17, 16, 15, 14, 13, 12
20
Q0 to Q7
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
FUNCTION TABLE
INPUTS
CP
OUTPUTS
OPERATING
MODES
INTERNAL
FLIP-FLOPS
OE
Dn
Q0 to Q7
load and read
register
L
L
↑
↑
l
h
L
H
H
L
load register and
disable outputs
H
H
↑
↑
l
h
L
H
Z
Z
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH
CP transition
Z = high impedance OFF-state
↑ = LOW-to-HIGH clock transition
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
50
18
14
165
33
28
205
41
35
250
50
43
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
Fig.6
t
t
t
PZH/ tPZL 3-state output enable
44
16
13
140
28
24
175
35
30
210
42
36
2.0
4.5
6.0
Fig.8
Fig.8
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
time
OE to Qn
PHZ/ tPLZ 3-state output disable
50
18
14
135
27
23
170
34
29
205
41
35
2.0
4.5
6.0
time
OE to Qn
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
2.0
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
2.0
4.5
6.0
tsu
set-up time
Dn to CP
60
12
10
6
2
2
75
15
13
90
18
15
2.0
4.5
6.0
th
hold time
Dn to CP
5
5
5
0
0
0
5
5
5
5
5
5
2.0
4.5
6.0
fmax
maximum clock pulse
frequency
6.0
30
35
38
115
137
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
OE
D0 to D7
CP
0.80
0.25
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
19
19
19
5
35
35
30
12
44
44
38
15
53
53
45
18
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.8
4.5 Fig.8
4.5 Fig.6
4.5 Fig.6
4.5 Fig.7
4.5 Fig.7
tPZH/ tPZL 3-state output enable
time OE to Qn
t
PHZ/ tPLZ 3-state output disable
time OE to Qn
tTHL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
18
12
3
8
23
15
3
27
18
3
tsu
th
set-up time
Dn to CP
3
hold time
Dn to CP
−2
56
fmax
maximum clock pulse
frequency
27
22
18
MHz 4.5 Fig.6
December 1990
6
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
AC WAVEFORMS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the data set-up and
hold times for the data input (Dn).
Fig.6 Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width, the output transition times and
the maximum clock pulse frequency.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the 3-state enable and
disable times.
December 1990
7
相关型号：
©2020 ICPDF网 联系我们和版权申明