74HCT574D,653 [NXP]
74HC(T)574 - Octal D-type flip-flop; positive edge-trigger; 3-state SOP 20-Pin;
| 型号： | 74HCT574D,653 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)574 - Octal D-type flip-flop; positive edge-trigger; 3-state SOP 20-Pin 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总19页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 5 — 25 April 2012
Product data sheet
1. General description
The 74HC574; 74HCT574 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC574; 74HCT574 are octal D-type flip-flops featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus-oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their
individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition. When OE is LOW the contents of the 8 flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of
the OE input does not affect the state of the flip-flops.
The 74HC574; 74HCT574 is functionally identical to:
• 74HC564: but has non-inverting outputs
• 74HC374; 74HCT374: but has a different pin arrangement
2. Features and benefits
3-state non-inverting outputs for bus oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC574N
74HCT574N
74HC574D
74HCT574D
−40 °C to +125 °C
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Table 1.
Ordering information …continued
Type number Package
Temperature range Name
Description
Version
74HC574DB
−40 °C to +125 °C
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74HCT574DB
74HC574PW −40 °C to +125 °C
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74HCT574PW
4. Functional diagram
D0
2
Q0
19
Q1 18
17
3
4
5
6
7
8
9
D1
D2
D3
D4
D5
D6
D7
Q2
FF1
to
FF8
Q3 16
Q4 15
3-STATE
OUTPUTS
Q5
14
Q6 13
Q7 12
CP
OE
11
1
mna800
Fig 1. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aah077
Fig 2. Logic diagram
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
2 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
11
C1
1
EN
11
CP
2
19
1D
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
4
5
18
17
16
6
7
8
9
15
14
13
12
OE
1
mna798
mna446
Fig 3. Logic symbol
Fig 4. IEC logic symbol
5. Pinning information
5.1 Pinning
74HC574
74HCT574
1
2
20
19
18
17
16
15
14
13
12
11
OE
D0
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
74HC574
74HCT574
3
D1
1
2
20
19
18
17
16
15
14
13
12
11
OE
D0
V
CC
4
D2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
5
D3
3
D1
4
D2
6
D4
5
D3
7
D5
6
D4
8
D6
7
D5
8
D6
9
D7
9
D7
10
GND
10
GND
001aan290
001aan291
Fig 5. Pin configuration DIP20 and SO20
Fig 6. Pin configuration SSOP20 and TSSOP20
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
3 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
3-state output enable input (active LOW)
data input
D[0:7]
GND
CP
2, 3, 4, 5, 6, 7, 8, 9
10
11
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
Q[0:7]
VCC
19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output
20
supply voltage
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
OE
L
Internal
flip-flop
Output
CP
↑
Dn
Qn
L
Load and read register
Load register and disable output
l
L
L
↑
h
l
H
L
H
Z
H
↑
H
↑
h
H
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
−0.5
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
-
20
mA
mA
mA
mA
mA
°C
IOK
-
20
IO
-
35
ICC
supply current
-
+70
−70
+150
750
500
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
−65
[1]
[2]
DIP20 package
-
-
mW
mW
SO20, SSOP20 and TSSOP20 packages
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO20: Ptot derates linearly with 8 mW/K above 70 °C.
For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
4 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC574
74HCT574
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
−40
+25
−40
+25
°C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ
−40 °C to +85 °C −40 °C to +125 °C Unit
Max
Min
Max
Min
Max
74HC574
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −20 μA; VCC = 2.0 V
IO = −20 μA; VCC = 4.5 V
IO = −20 μA; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = −6.0 mA; VCC = 4.5 V 3.98 4.32
IO = −7.8 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1.0
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
μA
IOZ
OFF-state
VI = VIH or VIL;
-
-
0.5
-
5.0
-
10.0 μA
output current VO = VCC or GND;
VCC = 6.0 V
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
5 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ
Max
Min
Max
Min
Max
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
μA
CI
input
-
3.5
-
pF
capacitance
74HCT574
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 μA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = −6 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA
-
-
-
0
0.1
-
-
-
0.1
0.33
1.0
-
-
-
0.1
0.4
1.0
V
IO = 6.0 mA
0.16 0.26
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
μA
IOZ
OFF-state
VI = VIH or VIL; VCC = 5.5 V;
-
-
0.5
-
5.0
-
10
μA
μA
output current VO = VCC or GND per input
pin; other inputs at VCC or
GND; IO = 0 A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160
ΔICC
additional
VI = VCC − 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; Dn inputs
per input pin; OE input
per input pin; CP input
-
-
-
-
50
180
450
540
-
-
-
-
225
563
675
-
-
-
245
613
735
μA
μA
μA
pF
125
150
3.5
CI
input
capacitance
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
6 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions
For type 74HC574
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ Max Min
Max
Min
Max
[1]
tpd
propagation CP to Qn; see Figure 7
delay
VCC = 2.0 V
-
-
-
-
47
17
14
14
150
30
-
-
-
-
-
190
35
-
-
-
-
-
225
45
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
33
38
[2]
[3]
[4]
ten
tdis
tt
enable time OE to Qn; see Figure 9
VCC = 2.0 V
-
-
-
44
16
13
140
28
-
-
-
175
35
-
-
-
210
42
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
24
30
36
disable time OE to Qn; see Figure 9
VCC = 2.0 V
-
-
-
39
14
11
125
25
-
-
-
155
31
-
-
-
190
38
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
21
26
32
transition
time
Qn; see Figure 7
VCC = 2.0 V
-
-
-
14
5
60
12
10
-
-
-
75
15
13
-
-
-
90
18
15
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
tW
pulse width CP HIGH or LOW;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
4
17
20
tsu
set-up time Dn to CP; see Figure 8
VCC = 2.0 V
60
12
10
6
2
2
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
th
hold time
Dn to CP; see Figure 8
VCC = 2.0 V
5
5
5
0
0
0
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum
frequency
CP; see Figure 7
VCC = 2.0 V
6.0
30
-
37
-
-
-
-
4.8
24
-
-
-
-
-
4.0
20
-
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 4.5 V
112
123
133
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
35
28
24
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
7 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Typ Max Min
Min
Max
Min
Max
[5]
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
-
22
-
-
-
-
-
pF
For type 74HCT574
[1]
tpd
propagation CP to Qn; see Figure 7
delay
VCC = 4.5 V
-
-
18
15
33
-
-
-
41
-
-
-
50
-
ns
ns
VCC = 5 V; CL = 15 pF
enable time OE to Qn; see Figure 9
VCC = 4.5 V
[2]
[3]
[4]
ten
tdis
tt
-
-
-
19
16
5
33
28
12
-
-
-
41
35
15
-
-
-
50
42
18
ns
ns
ns
disable time OE to Qn; see Figure 9
VCC = 4.5 V
transition
time
Qn; see Figure 7
VCC = 4.5 V
tW
pulse width CP HIGH or LOW;
see Figure 8
VCC = 4.5 V
set-up time Dn to CP; see Figure 8
VCC = 4.5 V
16
12
5
7
3
-
-
-
20
15
5
-
-
-
24
18
5
-
-
-
ns
ns
ns
tsu
th
hold time
Dn to CP; see Figure 8
VCC = 4.5 V
−1
fmax
maximum
frequency
CP; see Figure 7
VCC = 4.5 V
30
-
69
76
25
-
-
-
24
-
-
-
-
20
-
-
-
-
MHz
MHz
pF
VCC = 5 V; CL = 15 pF
[5]
CPD
power
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
-
-
-
dissipation
capacitance
[1] tpd is the same as tPLH and tPHL
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL × VCC2 × fo) = sum of outputs.
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
8 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
11. Waveforms
1/f
max
V
I
CP input
GND
V
M
t
t
W
t
PHL
PLH
V
OH
90 %
V
Qn output
M
10 %
V
OL
t
t
THL
TLH
001aan292
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the
maximum frequency (CP)
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
Dn input
M
GND
V
OH
V
Qn output
M
V
OL
mna803
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
9 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
V
I
OE input
V
M
GND
t
t
PZL
PLZ
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aah078
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Enable and disable times
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC574
0.5VCC
1.3 V
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
74HCT574
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
10 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 10. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC574
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT574
open
GND
VCC
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
11 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
12. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 11. Package outline SOT146-1 (DIP20)
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
12 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 12. Package outline SOT163-1 (SO20)
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
13 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 13. Package outline SOT339-1 (SSOP20)
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
14 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 14. Package outline SOT360-1 (TSSOP20)
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
15 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
ESD
Description
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20120425 Product data sheet
Change notice
Supersedes
74HC_HCT574 v.5
Modifications:
-
74HC_HCT574 v.4
• VX and VY measurement points added to Table 8.
74HC_HCT574 v.4
Modifications:
20111219
Product data sheet
-
74HC_HCT574 v.3
• Legal pages updated.
74HC_HCT574 v.3
74HC_HCT574_CNV v.2
20101215
19970827
Product data sheet
Product specification
-
-
74HC_HCT574_CNV v.2
-
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
16 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
17 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 April 2012
18 of 19
74HC574; 74HCT574
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 April 2012
Document identifier: 74HC_HCT574
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