74HCT594DB [NXP]
8-bit shift register with output register; 8位的移位寄存器，输出寄存器
| 型号： | 74HCT594DB |
| 厂家： | 
NXP |
| 描述： | 8-bit shift register with output register |
| 文件： | 总10页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT594
8-bit shift register with output
register
December 1991
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
FEATURES
DESCRIPTION
The 74HC/HCT594 are high-speed, Si-gate CMOS
devices, and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74HC/HCT594 contain an 8-bit, non-inverting,
serial-in, parallel-out shift register that feeds an 8-bit
D-type storage register. Separate clocks and direct
overriding clears are provided on both the shift and storage
registers. A serial output (Q7’) is provided for cascading
purposes.
• Synchronous serial input and output
• 8-bit parallel output
• Shift and storage register have independent direct clear
and clocks
• 100 MHz (typ.)
• Output capability:
– parallel outputs: bus driver
– serial outputs: standard
• ICC category: MSI
Both the shift and storage register clocks are positive-edge
triggered. If the user wishes to connect both clocks
together, the shift register will always be one count pulse
ahead of the storage register.
APPLICATIONS
• Serial-to parallel data conversion
• Remote control holding register
QUICK REFERENCE DATA
GND = 0 V: Tamb = 250 C; tr = tf = 6 ns.
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
t
PHL/tPLH
CL = 15 pF; VCC = 5 V
SHCP to Q7’
13
15
ns
STCP to Qn
13
15
ns
SHR to Qn
11
14
ns
STR to Qn
11
14
ns
fmax
CI
maximum clock frequency SHCP, STCP
input capacitance
100
3.5
84
100
3.5
89
MHz
pF
pF
CPD
power dissipation capacitance per package notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo), where:
fi = input frequency in MHz; fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of the outputs;
CL = output load capacitance in pF; VCC = supply voltage in V.
2. For HC, the condition is VI = GND to VCC; for HCT, the condition is VI = GND to VCC − 1.5 V.
ORDERING INFORMATION
PACKAGES
EXTENDED TYPE NUMBER
PINS
16
PIN POSITION
MATERIAL
plastic
CODE
PC74HC/HCT594P
PC74HC/HCT594T
DIL
SO
SOT38C, P
SOT109A
16
plastic
December 1991
2
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
PINNING
SYMBOL
Q0 to Q7
PIN
15 & 1 to 7
DESCRIPTION
parallel data outputs
ground (0 V)
GND
Q7’
8
9
serial data output
SHR
SHCP
STCP
STR
Ds
10
11
12
13
14
16
shift register reset (active LOW)
shift register clock input
storage register clock input
storage register reset active (LOW)
serial data input
VCC
supply voltage
11
SH
12
ST
halfpage
ge
13
ST
R
2
R
ge
12
10
11
V
16
1
2
3
4
CP
CP
Q
Q
ST
SH
C2
CC
0
1
2
CP
9
Q '
7
0
1
SH
R
1
SRG8
C1/
R
15 Q
14
15
1
Q
Q
CP
Q
Q
Q
Q
Q
D
3
4
5
6
7
S
14
15
1
D
S
Q
1D
2D
0
2
Q
Q
Q
Q
Q
Q
13
12
2
3
4
5
6
7
ST
ST
R
Q
Q
Q
Q
Q
Q
Q
1
2
3
4
5
6
7
3
14
D
S
594
2
5
6
7
8
CP
CP
4
3
11 SH
4
5
5
6
10
SH
R
6
7
9
Q '
GND
7
7
SH
ST
R
R
MBC318
9
Q '
7
10
13
MBC319
MBC322 - 1
Fig.1 Logic symbol.
Fig.2 Pin configuration.
Fig.3 IEC logic symbol.
December 1991
3
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
handbook, halfpage
D
14
11
10
S
SH
CP
8-STAGE SHIFT REGISTER
8-BIT STORAGE REGISTER
SH
R
Q '
7
9
ST
ST
12
13
CP
R
Q
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
0
1
2
3
4
5
6
7
15
MBC320
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
SHCP STCP SHR
OUTPUTS
FUNCTION
STR
DS
Q7’
Qn
X
X
X
↑
X
X
↑
L
X
X
X
X
H
L
NC
L
a LOW level on SHR only affects the shift registers.
a LOW level on STR only affects the storage registers.
empty shift register loaded into storage register.
X
L
L
NC
L
H
X
L
X
H
Q6’
NC
logic HIGH level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage
6 (internal Q6’) appears on the serial output (Q7’).
X
↑
↑
H
H
H
H
X
X
NC
Qn’
contents of shift register stages (internal Qn’) are transferred to
the storage register and parallel output stages.
↑
Q6n Qn’
contents of shift register shifted through. Previous contents of
shift register transferred to the storage register and the parallel
output stages.
Note
1. H = HIGH voltage level
L = LOW voltage level
↑ = LOW-to-HIGH transition
NC = no change
X = don’t care.
December 1991
4
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
STAGE 0
STAGES 1 TO
STAGE 7
6
D
D
Q '
7
Q
D
Q
D
Q
7
S
FFSH
FFSH
0
CP
CP
R
R
SH
CP
SH
R
D
FFST
D
FFST
CP
Q
Q
7
0
CP
R
R
ST
CP
ST
R
MBC321 - 1
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
Fig.5 Logic diagram.
SH
CP
D
S
ST
CP
SH
R
ST
R
Q
0
Q
1
Q
6
Q
7
Q '
7
MBC323 - 1
Fig.6 Timing diagram.
5
December 1991
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
DC CHARACTERISTICS FOR 74HC
For the DC characteristics, see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: parallel outputs, bus driver; serial output, standard.
ICC category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
+25
−40 to +85 −40 to +125 UNIT VCC
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/tPLH propagation delay
SHCP to Q7’
−
−
−
44
16
14
150
30
26
−
−
−
185
37
31
−
−
−
225
45
38
ns
ns
ns
2.0 Fig.7
4.5
6.0
propagation delay
STCP to Qn
−
−
−
44
16
14
150
30
26
−
−
−
185
37
31
−
−
−
225
45
38
ns
ns
ns
2.0 Fig.8
4.5
6.0
tPHL
propagation delay
SHR to Q7’
−
−
−
39
14
12
150
30
26
−
−
−
185
37
31
−
−
−
225
45
38
ns
ns
ns
2.0 Fig.11
4.5
6.0
propagation delay
STR to Qn
−
−
−
39
14
12
125
25
21
−
−
−
155
31
26
−
−
−
185
37
31
ns
ns
ns
2.0 Fig.12
4.5
6.0
tW
shift clock pulse width 80
10
4
3
−
−
−
100
20
17
−
−
−
120
24
20
−
−
−
ns
ns
ns
2.0 Fig.7
4.5
6.0
HIGH or LOW
16
14
storage clock pulse
width HIGH or LOW
80
16
14
10
4
3
−
−
−
100
20
17
−
−
−
120
24
20
−
−
−
ns
ns
ns
2.0 Fig.8
4.5
6.0
shift and storage reset 80
14
5
4
−
−
−
100
20
17
−
−
−
120
24
20
−
−
−
ns
ns
ns
2.0 Fig.11 and Fig.12
4.5
6.0
pulse width HIGH or
LOW
16
14
tsu
set-up time
Ds to SHCP
100 10
−
−
−
125
25
21
−
−
−
150
30
26
−
−
−
ns
ns
ns
2.0 Fig.9
4.5
6.0
20
17
4
3
set-up time
SHR to STCP
100 14
−
−
−
125
25
21
−
−
−
150
30
26
−
−
−
ns
ns
ns
2.0 Fig.10
4.5
6.0
20
17
5
4
set-up time
SHCP to STCP
100 17
−
−
−
125
25
21
−
−
−
150
30
26
−
−
−
ns
ns
ns
2.0 Fig.8
4.5
6.0
20
17
6
5
December 1991
6
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
T
amb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
+25
−40 to +85 −40 to +125 UNIT VCC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
th
hold time Ds to SHCP 25
−8
−3
−2
−
−
−
30
6
5
−
−
−
35
7
6
−
−
−
ns
ns
ns
2.0 Fig.9
4.5
6.0
5
4
trem
removal time
SHR to SHCP
STR to STCP
50
10
9
−14
−5
−4
−
−
−
65
13
11
−
−
−
75
15
13
−
−
−
ns
ns
ns
2.0 Fig.11 and Fig.12
4.5
6.0
,
fmax
maximum clock
frequency
SHCP or STCP
6.0
30
35
30
92
109
−
−
−
4.8
24
28
−
−
−
4.0
20
24
−
−
−
MHz 2.0 Fig.7 and Fig.8
MHz 4.5
MHz 6.0
December 1991
7
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
DC CHARACTERISTICS FOR
74HCT
Note to HCT types
The value of additional quiescent
supply current (∆ICC) for a unit load of
1 is given in the family specifications.
To determine ∆ICC per input, multiply
this value by the unit load coefficient
shown in the following table.
UNIT LOAD
COEFFICIENT
INPUT
For the DC characteristics, see
“74HC/HCT/HCU/HCMOS Logic
Family Specifications”.
Ds
0.25
1.50
1.50
1.50
1.50
SHR
Output capability: parallel outputs,
bus driver; serial output, standard.
SHCP
STCP
STR
ICC category: MSI.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
+25
−40 to +85 −40 to +125 UNIT VCC WAVEFORMS
(V)
min. typ. max. min. max. min. max.
t
PHL/tPLH propagation delay
−
18
18
17
17
4
32
32
30
30
−
−
40
40
38
38
−
−
48
48
45
45
−
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
SHCP to Q7’
propagation delay
STCP to Qn
−
−
−
4.5 Fig.8
tPHL
propagation delay
SHR to Q7’
−
−
−
4.5 Fig.11
4.5 Fig.12
4.5 Fig.7
propagation delay
STR to Qn
−
−
−
tW
shift clock pulse width
HIGH or LOW
16
16
20
20
20
24
24
24
storage clock pulse
width HIGH or LOW
4
−
−
−
4.5 Fig.8
shift and storage reset 16
pulse width HIGH or
LOW
6
−
−
−
4.5 Fig.11 and Fig.12
tsu
set-up time Ds to SHCP 20
4
−
−
−
−
−
25
25
25
6
−
−
−
−
−
30
30
30
7
−
−
−
−
−
ns
ns
ns
ns
ns
4.5 Fig.9
set-up time
SHR to STCP
20
20
5
6
4.5 Fig.10
set-up time
SHCP to STCP
7
4.5 Fig.8
th
hold time Ds to SHCP
−3
−5
4.5 Fig.9
trem
removal time
10
13
15
4.5 Fig.11 and Fig.12
SHR to SHCP
,
STR to STCP
fmax
maximum clock
frequency
SHCP or STCP
30
92
−
24
8
−
20
−
MHz 4.5 Fig.7 and Fig.8
December 1991
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
AC WAVEFORMS
(1)
SH
ST
INPUT
INPUT
V
CP
M
t
su
1/ f
max
(1)
t
V
t
CP
M
W
t
PHL
PLH
Q
OUTPUTS
n
(1)
V
M
MLA512
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V
Fig.8 Waveforms showing the storage clock
Fig.7 Waveforms showing the shift clock
(SHCP) to output (Q7’) propagation delays,
the shift clock pulse width and the maximum
shift clock frequency.
(STCP) to output (Qn) propagation delays,
the storage clock pulse width, maximum
storage clock frequency and the shift clock
to storage clock set-up time.
handbook, halfpage
(1)
V
SH INPUT
M
R
t
su
(1)
V
ST
INPUT
M
CP
(1)
V
Q
OUTPUTS
M
n
MBC326
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V
Fig.9 Waveforms showing the data set-up and
hold times for the Ds input.
Fig.10 Waveforms showing the set-up time from
shift reset (SHR) to storage clock (STCP).
December 1991
9
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
handbook, halfpage
(1)
handbook, halfpage
(1)
t
V
V
M
SH INPUT
ST INPUT
R
M
R
t
W
W
t
t
rem
(1)
rem
(1)
V
V
M
SH
INPUT
ST
INPUT
CP
M
CP
t
t
PHL
PHL
(1)
(1)
V
V
M
Q ' OUTPUT
Q
OUTPUTS
n
M
7
MBC324
MBC325 - 1
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V
Fig.12 Waveforms showing the storage reset
(STR) pulse width, the storage reset to
outputs (Qn) propagation delay and the
storage reset to storage clock
Fig.11 Waveforms showing the shift reset
(SHR) pulse width, the shift reset to output
(Q7’) propagation delay and the shift reset
to shift clock (SHCP) removal time.
(STCP) removal time.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1991
10
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NEXPERIA
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