74HCT595BQ,115 [NXP]
74HC(T)595 - 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state QFN 16-Pin;
| 型号： | 74HCT595BQ,115 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)595 - 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state QFN 16-Pin 输出元件 逻辑集成电路 触发器 |
| 文件： | 总24页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 6 — 12 December 2011
Product data sheet
1. General description
The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7A.
The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
2. Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC595N
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HCT595N
74HC595D
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT338-1
SOT403-1
SOT763-1
74HCT595D
74HC595DB
74HCT595DB
74HC595PW
74HCT595PW
74HC595BQ
74HCT595BQ
SSOP16
TSSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
5. Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
9
12 STCP
13 OE
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
Q0
15
Q1 Q2 Q3 Q4 Q5 Q6 Q7
1
2
3
4
5
6
7
mna554
Fig 1. Functional diagram
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
2 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
13
EN3
12
C2
11
12
10
SHCP
STCP
SRG8
R
11
9
15
1
C1/
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
14
15
1
1D
2D
3
2
2
14
3
DS
3
4
4
5
5
6
6
7
Q7
OE
7
MR
10
9
13
mna552
mna553
Fig 2. Logic symbol
Fig 3. IEC logic symbol
STAGE 0
STAGES 1 TO 6
STAGE 7
DS
Q7S
D
Q
D
Q
D
Q
FF7
CP
FF0
CP
R
R
SHCP
MR
D
Q
D
Q
LATCH
CP
LATCH
CP
STCP
OE
mna555
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig 4. Logic diagram
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
3 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6. Pinning information
6.1 Pinning
74HC595
74HCT595
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1
Q2
V
CC
74HC595
74HCT595
Q0
Q3
DS
1
2
3
4
5
6
7
8
16
15
14
13
Q1
Q2
V
CC
Q0
DS
OE
Q4
OE
Q3
Q5
STCP
SHCP
MR
Q4
12 STCP
Q6
Q5
11
10
9
Q6
SHCP
MR
Q7
Q7
GND
Q7S
GND
Q7S
001aao241
001aao242
Fig 5. Pin configuration DIP16, SO16
Fig 6. Pin configuration SSOP16, TSSOP16
74HC595
74HCT595
terminal 1
index area
2
3
4
5
6
7
15
14
13
12
11
10
Q2
Q0
Q3
Q4
Q5
Q6
Q7
DS
OE
STCP
SHCP
MR
(1)
GND
001aao243
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 7. Pin configuration for DHVQFN16
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
4 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6.2 Pin description
Table 2.
Symbol
Q1
Pin description
Pin
1
Description
parallel data output 1
parallel data output 2
parallel data output 3
parallel data output 4
parallel data output 5
parallel data output 6
parallel data output 7
ground (0 V)
Q2
2
Q3
3
Q4
4
Q5
5
Q6
6
Q7
7
GND
Q7S
MR
8
9
serial data output
10
11
12
13
14
15
16
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
SHCP
STCP
OE
DS
Q0
parallel data output 0
supply voltage
VCC
7. Functional description
Table 3.
Control
Function table[1]
Input Output
Function
SHCP STCP OE
MR
L
DS
X
Q7S
L
Qn
NC
L
X
X
X
X
X
X
L
L
H
L
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
L
X
L
L
X
L
Z
shift register clear; parallel outputs in high-impedance OFF-state
H
H
Q6S
NC
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X
L
L
H
H
X
X
NC
QnS
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
Q6S
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1] H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
5 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
SHCP
DS
STCP
MR
OE
Q0
Z-state
Z-state
Q1
Z-state
Z-state
Q6
Q7
Q7S
mna556
Fig 8. Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
pin Q7S
-
-
20
20
mA
mA
IOK
IO
-
25
35
70
mA
mA
mA
mA
C
pins Qn
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
70
65
-
storage temperature
total power dissipation
DIP16 package
+150
[1]
[2]
[3]
[3]
[4]
-
-
-
-
-
750
500
500
500
500
mW
mW
mW
mW
mW
SO16 package
SSOP16 package
TSSOP16 package
DHVQFN16 package
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
6 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
74HC595
74HCT595
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
-
VCC
VI
supply voltage
input voltage
output voltage
2.0
5.0
4.5
5.0
V
0
-
VCC
VCC
625
139
83
0
-
V
VO
0
-
-
0
-
-
V
t/V
input transition rise and
fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
ns/V
-
-
1.67
-
-
-
1.67
-
139 ns/V
ns/V
+125 C
-
Tamb
ambient temperature
40
+25
+125
40
+25
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ
Max
Min
Max
74HC595
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
all outputs
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
Q7S output
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
1.9
4.4
5.9
-
-
-
V
V
V
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
Qn bus driver outputs
IO = 6 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
3.84
5.34
4.32
5.81
-
-
3.7
5.2
-
-
V
V
3.84
5.34
4.32
5.81
-
-
3.7
5.2
-
-
V
V
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
7 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ
Max
Min
Max
VOL
LOW-level
VI = VIH or VIL
output voltage
all outputs
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
Q7S output
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
0.1
0.1
0.1
V
V
V
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
Qn bus driver outputs
IO = 6 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
0.15
0.16
0.33
0.33
-
-
0.4
0.4
V
V
-
-
-
0.15
0.16
-
0.33
0.33
1.0
-
-
-
0.4
0.4
V
V
II
input leakage
current
1.0
A
IOZ
ICC
CI
OFF-state
output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
-
-
-
-
-
5.0
80
-
-
-
-
10
160
-
A
A
pF
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
input
3.5
capacitance
74HCT595
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
all outputs
IO = 20 A
4.4
3.84
3.7
4.5
-
-
-
4.4
3.7
3.7
-
-
-
V
V
V
Q7S output
IO = 4 mA
4.32
4.32
Qn bus driver outputs
IO = 6 mA
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
all outputs
IO = 20 A
-
-
0
0.1
-
-
0.1
0.4
V
V
Q7S output
IO = 4.0 mA
0.15
0.33
Qn bus driver outputs
IO = 6.0 mA
-
-
0.16
-
0.33
-
-
0.4
V
II
input leakage
current
VI = VCC or GND; VCC = 5.5 V
1.0
1.0
A
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
8 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ
Max
Min
Max
IOZ
OFF-state
output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND
-
-
5.0
-
10
A
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
-
-
80
-
160
VCC = 5.5 V
ICC
additional
per input pin; IO = 0 A; VI = VCC
supply current
2.1 V; other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pins MR, SHCP, STCP, OE
pin DS
-
-
-
150
25
675
113
-
-
-
-
735
123
-
A
A
pF
CI
input
3.5
capacitance
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
9 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions
74HC595
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min
Max
Min
Max
[2]
[2]
[3]
[4]
[5]
tpd
propagation SHCP to Q7S; see Figure 9
delay
VCC = 2 V
-
-
-
52
19
15
160
32
-
-
-
200
40
-
-
-
240
48
ns
ns
ns
VCC = 4.5 V
VCC = 6 V
27
34
41
STCP to Qn; see Figure 10
VCC = 2 V
-
-
-
55
20
16
175
35
-
-
-
220
44
-
-
-
265
53
ns
ns
ns
VCC = 4.5 V
VCC = 6 V
30
37
45
MR to Q7S; see Figure 12
VCC = 2 V
-
-
-
47
17
14
175
35
-
-
-
220
44
-
-
-
265
53
ns
ns
ns
VCC = 4.5 V
VCC = 6 V
30
37
45
ten
tdis
tW
enable time OE to Qn; see Figure 13
VCC = 2 V
-
-
-
47
17
14
150
30
-
-
-
190
38
-
-
-
225
45
ns
ns
ns
V
CC = 4.5 V
VCC = 6 V
disable time OE to Qn; see Figure 13
VCC = 2 V
26
33
38
-
-
-
41
15
12
150
30
-
-
-
190
38
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6 V
27
33
38
pulse width SHCP HIGH or LOW;
see Figure 9
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
75
15
13
17
6
-
-
-
95
19
16
-
-
-
110
22
-
-
-
ns
ns
ns
5
19
STCP HIGH or LOW;
see Figure 10
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
75
15
13
11
4
-
-
-
95
19
16
-
-
-
110
22
-
-
-
ns
ns
ns
3
19
MR LOW; see Figure 12
VCC = 2 V
75
15
13
17
6
-
-
-
95
19
16
-
-
-
110
22
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6 V
5
19
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
10 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min
Max
Min
Max
tsu
set-up time DS to SHCP; see Figure 10
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
50
10
9
11
4
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
3
SHCP to STCP;
see Figure 11
VCC = 2 V
75
15
13
22
8
-
-
-
95
19
16
-
-
-
110
22
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6 V
7
19
th
hold time
DS to SHCP; see Figure 11
VCC = 2 V
3
3
3
6
2
2
-
-
-
3
3
3
-
-
-
3
3
3
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6 V
trec
recovery
time
MR to SHCP; see Figure 12
VCC = 2 V
50
10
9
19
7
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6 V
6
fmax
maximum
frequency
SHCP or STCP;
see Figure 9 and 10
VCC = 2 V
9
30
35
-
30
91
-
-
-
-
4.8
24
28
-
-
-
-
-
4
20
24
-
-
-
-
-
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 6 V
108
115
[6][7]
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
74HCT595; VCC = 4.5 V to 5.5 V
[2]
[2]
[3]
[4]
[5]
tpd
propagation SHCP to Q7S; see Figure 9
-
-
25
24
23
21
18
6
42
40
40
35
30
-
-
-
53
50
50
44
38
-
-
-
63
60
60
53
45
-
ns
ns
ns
ns
ns
ns
delay
STCP to Qn; see Figure 10
MR to Q7S; see Figure 12
-
-
-
ten
tdis
tW
enable time OE to Qn; see Figure 13
disable time OE to Qn; see Figure 13
-
-
-
-
-
-
pulse width SHCP HIGH or LOW;
see Figure 9
16
20
24
STCP HIGH or LOW;
see Figure 10
16
5
-
20
-
24
-
ns
MR LOW; see Figure 12
20
16
16
8
5
8
-
-
-
25
20
20
-
-
-
30
24
24
-
-
-
ns
ns
ns
tsu
set-up time DS to SHCP; see Figure 10
SHCP to STCP;
see Figure 11
th
hold time
DS to SHCP; see Figure 11
3
2
-
3
-
3
-
ns
74HC_HCT595
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Product data sheet
Rev. 6 — 12 December 2011
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74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min
Max
Min
Max
trec
recovery
time
MR to SHCP; see Figure 12
10
30
-
7
52
-
-
-
13
24
-
-
15
-
ns
fmax
CPD
maximum
frequency
SHCP and STCP;
see Figure 9 and 10
-
-
20
-
-
-
MHz
pF
[6]
[7]
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
130
[1] Typical values are measured at nominal supply voltage.
[2]
t
pd is the same as tPHL and tPLH
.
[3] tpd is the same as tPHL only.
[4] ten is the same as tPZL and tPZH
.
[5]
tdis is the same as tPLZ and tPHZ.
[6] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
[7] All 9 outputs switching.
12. Waveforms
1/f
max
V
I
SHCP input
GND
V
M
t
t
W
t
PHL
PLH
V
OH
V
Q7S output
M
V
OL
mna557
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. Shift clock pulse, maximum frequency and input to output propagation delays
74HC_HCT595
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Product data sheet
Rev. 6 — 12 December 2011
12 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
V
I
SHCP input
GND
V
M
t
1/f
max
su
V
I
STCP input
GND
V
M
t
t
W
t
PHL
PLH
V
OH
V
Qn output
M
V
OL
mna558
Measurement points are given in Table 8.
OL and VOH are typical output voltage levels that occur with the output load.
V
Fig 10. Storage clock to output propagation delays
V
I
V
SHCP input
M
GND
t
t
su
su
M
t
t
h
h
V
I
V
DS input
GND
V
OH
V
Q7S output
M
V
OL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Data set-up and hold times
74HC_HCT595
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Product data sheet
Rev. 6 — 12 December 2011
13 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
V
I
V
M
MR input
GND
t
t
rec
W
V
I
SHCP input
Q7S output
V
M
GND
t
PHL
V
OH
V
M
V
OL
mna561
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Master reset to output propagation delays
t
r
t
f
90 %
V
OE input
M
10 %
t
t
PZL
PLZ
Qn output
V
LOW-to-OFF
OFF-to-LOW
M
10 %
t
t
PHZ
PZH
90 %
Qn output
V
HIGH-to-OFF
OFF-to-HIGH
M
outputs
enabled
outputs
enabled
outputs
disabled
msa697
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. Enable and disable times
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC595
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT595
74HC_HCT595
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Product data sheet
Rev. 6 — 12 December 2011
14 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
t
W
V
I
90 %
negative
pulse
V
M
V
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Fig 14. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
Load
CL
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC595
VCC
3 V
50 pF
50 pF
1 k
1 k
74HCT595
open
GND
VCC
74HC_HCT595
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Product data sheet
Rev. 6 — 12 December 2011
15 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 15. Package outline SOT38-4 (DIP16)
74HC_HCT595
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
16 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 16. Package outline SOT109-1 (SO16)
74HC_HCT595
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Product data sheet
Rev. 6 — 12 December 2011
17 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 17. Package outline SOT338-1 (SSOP16)
74HC_HCT595
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
18 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 18. Package outline SOT403-1 (TSSOP16)
74HC_HCT595
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Product data sheet
Rev. 6 — 12 December 2011
19 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 19. Package outline SOT763-1 (DHVQFN16)
74HC_HCT595
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Product data sheet
Rev. 6 — 12 December 2011
20 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
14. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Abbreviation
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
15. Revision history
Table 11. Revision history
Document ID
Release date
20111212
Data sheet status
Change notice
Supersedes
74HC_HCT595 v.6
Modifications:
Product data sheet
-
74HC_HCT595 v.5
• Legal pages updated.
74HC_HCT595 v.5
74HC_HCT595 v.4
20110628
Product data sheet
-
-
-
74HC_HCT595 v.4
20030604
Product specification
Product specification
74HC_HCT595_CNV v.3
-
74HC_HCT595_CNV v.3 19980604
74HC_HCT595
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Product data sheet
Rev. 6 — 12 December 2011
21 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
22 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
23 of 24
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 December 2011
Document identifier: 74HC_HCT595
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