74HCT595D [NXP]
8-bit serial-in/serial or parallel-out shift register with output latches; 3-state; 8位串行输入/串行或并行输出移位寄存器与输出锁存器;三态
| 型号： | 74HCT595D |
| 厂家： | 
NXP |
| 描述： | 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state |
| 文件： | 总20页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
1998 Jun 04
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
FEATURES
DESCRIPTION
• 8-bit serial input
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• 100 MHz (typ) shift out frequency
• Output capability:
The “595” is an 8-stage serial shift register with a storage
register and 3-state outputs. The shift register and storage
register have separate clocks.
– parallel outputs; bus driver
– serial output; standard
• ICC category: MSI.
Data is shifted on the positive-going transitions of the
SHCP input. The data in each register is transferred to the
storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register.
The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
TYP.
SYMBOL PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/tPLH propagation delay
CL = 15 pF; VCC = 5 V
SHCP to Q7’
16
21
ns
STCP to Qn
17
20
ns
MR to Q7’
14
19
ns
fmax
CI
maximum clock frequency SHCP, STCP
input capacitance
100
3.5
115
57
MHz
pF
pF
3.5
130
CPD
power dissipation capacitance per package
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V.
1998 Jun 04
2
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
74HC595N
74HC595D
74HC595DB
74HC595PW
74HCT595N
74HCT595D
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-1
SO16
SOT109-1
SSOP16
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil); long body
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-1
SOT109-1
PINNING
SYMBOL
PIN
DESCRIPTION
Q0 to Q7
GND
Q7’
15, 1 to 7
parallel data output
ground (0 V)
8
9
serial data output
MR
10
11
12
13
14
16
master reset (active LOW)
shift register clock input
SHCP
STCP
OE
storage register clock input
output enable (active LOW)
serial data input
DS
VCC
positive supply voltage
handbook, halfpage
11
12
handbook, halfpage
SH
ST
1
2
3
4
5
6
7
8
16
15
14
Q
Q
Q
Q
Q
Q
Q
V
CC
CP
CP
1
2
3
4
5
6
7
9
15
1
Q '
7
Q
D
0
Q
0
S
Q
1
2
13 OE
Q
2
595
3
14
ST
12
Q
3
D
CP
S
4
Q
4
SH
11
10 MR
Q '
CP
5
Q
5
6
Q
6
7
GND
9
7
Q
7
MLA001
MR
10
OE
13
MLA002
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1998 Jun 04
3
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
13
12
10
11
handbook, halfpage
OE
EN3
C2
ST
CP
R
MR
SRG8
C1/
SH
CP
14
15
1
1D
2D
Q
Q
Q
Q
Q
Q
Q
Q
3
D
S
0
1
2
3
4
5
6
7
2
3
4
5
6
7
9
Q '
7
MSA698
Fig.3 IEC logic symbol.
D
14
11
10
S
SH
CP
8-STAGE SHIFT REGISTER
8-BIT STORAGE REGISTER
MR
Q '
7
9
ST
12
CP
Q
0
1
2
3
4
5
6
7
15
1
Q
Q
Q
2
3
13 OE
Q
3-STATE OUTPUTS
4
Q
Q
5
6
Q
7
MLA003
Fig.4 Functional diagram.
4
1998 Jun 04
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
STAGE 0
STAGES 1 TO 6
STAGE 7
D
Q '
7
D
Q
D
Q
D
Q
S
FF0
FF7
CP
CP
R
R
SH
CP
MR
D
Q
D
Q
LATCH
CP
LATCH
CP
ST
CP
OE
Q
Q
Q
Q
Q
Q
Q
Q
7
MLA010
0
1
2
3
4
5
6
Fig.5 Logic diagram.
1998 Jun 04
5
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
FUNCTION TABLE
INPUTS
OE
OUTPUTS
FUNCTON
SHCP
STCP
MR
DS
Q7’
QN
X
X
X
X
↑
L
L
L
L
L
X
X
X
L
L
L
NC a LOW level on MR only affects the shift registers
L
Z
empty shift register loaded into storage register
X
H
shift register clear. Parallel outputs in high-impedance
OFF-state
↑
X
L
H
H
Q6’
NC logic high level shifted into shift register stage 0. Contents
of all shift register stages shifted through, e.g. previous
state of stage 6 (internal Q6’) appears on the serial output
(Q7’)
X
↑
↑
L
L
H
H
X
X
NC
Q6’
Qn’ contents of shift register stages (internal Qn’) are
transferred to the storage register and parallel output
stages
↑
Qn’ contents of shift register shifted through. Previous
contents of the shift register is transferred to the storage
register and the parallel output stages.
Notes
1. H = HIGH voltage level; L = LOW voltage level
↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Z = high-impedance OFF-state; NC = no change
X = don’t care.
1998 Jun 04
6
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
SH
CP
D
S
ST
CP
MR
OE
Q
0
high-impedance OFF-state
Q
1
Q
6
Q
7
Q '
7
MLA005 - 1
Fig.6 Timing diagram.
1998 Jun 04
7
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: parallel outputs, bus driver, serial output, standard ICC category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
T
amb (°C)
TEST CONDITION
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
min typ max min max min max
tPHL/tPLH
propagation delay
SHCP to Q7’
−
52
19
15
55
20
16
47
17
14
47
17
14
41
15
12
17
6
160
32
27
175
35
30
175
35
30
150
30
26
150
30
26
−
−
200
40
34
220
44
37
220
44
37
190
38
33
190
38
33
−
−
240
48
41
265
53
45
265
53
45
225
45
38
225
45
38
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.7
−
−
−
4.5
−
−
−
6.0
tPHL/tPLH
propagation delay
STCP to Qn
−
−
−
2.0 Fig.8
−
−
−
4.5
−
−
−
6.0
tPHL
propagation delay
MR to Q7’
−
−
−
2.0 Fig.10
−
−
−
4.5
−
−
−
6.0
tPZH/tPZL
3-state output
enable time
OE to Qn
−
−
−
2.0 Fig.11
−
−
−
4.5
−
−
−
6.0
tPHZ/tPLZ
3-state output
disable time
OE to Qn
−
−
−
2.0 Fig.11
−
−
−
4.5
−
−
−
6.0
tW
tW
tW
tsu
tsu
shift clock pulse
width HIGH or
LOW
75
15
13
75
15
13
75
15
13
50
10
9.0
75
15
13
95
19
16
95
19
16
95
19
16
65
13
11
95
19
16
110
22
19
110
22
19
110
22
19
75
15
13
110
22
19
2.0 Fig.7
−
−
−
4.5
5
−
−
−
6.0
storage clock
pulse width HIGH
or LOW
11
4
−
−
−
2.0 Fig.8
−
−
−
4.5
3
−
−
−
6.0
master reset
pulse width LOW
17
6.0
5.0
11
4.0
3.0
22
8
−
−
−
2.0 Fig.10
−
−
−
4.5
−
−
−
6.0
set-up time DS to
SHCP
−
−
−
2.0 Fig.9
4.5
−
−
−
−
−
−
6.0
set-up time SHCP
to STCP
−
−
−
2.0 Fig.8
4.5
−
−
−
7
−
−
−
6.0
1998 Jun 04
8
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
T
amb (°C)
TEST CONDITION
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
min typ max min max min max
th
hold time DS to
SHCP
3
−6
−
−
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
−
ns
ns
2.0 Fig.9
3
−2
3
3
4.5
3
−2
3
3
6.0
trem
removal time MR
to SHCP
50
10
9
−19
−7
65
13
11
4.8
24
28
75
15
13
4
2.0 Fig.10
4.5
6.0
−6
fmax
maximum clock
pulse frequency
SHCP or STCP
9
30
MHz 2.0 Figs 7 and 8
30
35
91
20
24
4.5
6.0
108
1998 Jun 04
9
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI.
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
INPUT
UNIT LOAD COEFFICIENT
0.25
DS
MR
1.50
1.50
1.50
1.50
SHCP
STCP
OE
1998 Jun 04
10
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
T
amb (°C)
−40 to +85 −40 to +125 UNIT
TEST CONDITION
SYMBOL PARAMETER
+25
min typ max min max min max
VCC
(V)
WAVEFORMS
tPHL/ tPLH propagation delay
SHCP to Q7’
−
25
24
23
21
18
6
42
40
40
35
30
−
−
53
50
50
44
38
−
−
63
60
60
53
45
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.8
4.5 Fig.10
4.5 Fig.11
4.5 Fig.11
4.5 Fig.7
4.5 Fig.8
4.5 Fig.10
4.5 Fig.9
4.5 Fig.8
4.5 Fig.9
4.5 Fig.10
t
PHL/ tPLH propagation delay
STCP to Qn
−
−
−
tPHL
propagation delay
MR to Q7’
−
−
−
t
t
PZH/ tPZL 3-state output enable
−
−
−
time OE to Qn
PHZ/ tPLZ 3-state output disable
time OE to Qn
−
−
−
tW
shift clock pulse
16
20
20
25
20
20
3
24
24
30
24
24
3
width HIGH or LOW
tW
storage clock pulse width 16
HIGH or LOW
5
−
−
−
tW
master reset
20
16
16
3
8
−
−
−
pulse width LOW
tsu
tsu
th
set-up time DS to
SHSP
5
−
−
−
set-up time SHCP
to STCP
8
−
−
−
hold time DS to SHCP
−2
−7
52
−
−
−
trem
fmax
removal time MR
to SHCP
10
30
−
13
24
−
15
20
−
maximum clock
pulse frequency
SHCP or STCP
−
−
−
MHz 4.5 Figs 7 and 8
1998 Jun 04
11
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
AC WAVEFORMS
1/f
max
(1)
V
SH
CP
INPUT
M
t
t
W
t
PLH
PHL
90%
(1)
t
V
Q ' OUTPUT
M
7
10%
t
MSA699
TLH
THL
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width and
maximum shift clock frequency.
(1)
V
t
SH
ST
INPUT
INPUT
M
CP
1/f
max
su
(1)
V
M
t
CP
t
W
t
PLH
PHL
(1)
V
Q
OUTPUT
M
n
MSA700
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse
width and the shift clock to storage clock set-up time.
1998 Jun 04
12
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
(1)
V
SH
CP
INPUT
M
t
t
su
su
t
t
h
h
(1)
D
INPUT
V
S
M
(1)
Q ' OUTPUT
7
V
M
MLB196
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the data set-up and hold times for the DS input.
(1)
V
MR INPUT
M
t
t
rem
W
(1)
SH
CP
INPUT
V
M
t
PHL
(1)
V
Q ' OUTPUT
M
7
MLB197
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7’) propagation delay
and the master reset to shift clock (SHCP) removal time.
1998 Jun 04
13
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
t
t
r
f
90%
(1)
V
OE INPUT
M
10%
t
t
PZL
PLZ
Q
OUTPUT
n
(1)
V
LOW-to-OFF
OFF-to-LOW
M
10%
t
t
PHZ
PZH
90%
Q
OUTPUT
n
(1)
V
HIGH-to-OFF
OFF-to-HIGH
M
outputs
enabled
outputs
enabled
outputs
disabled
MSA697
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the 3-state enable and disable times for input OE.
1998 Jun 04
14
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
max.
min.
max.
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
3.9
3.4
8.25
7.80
9.5
8.3
4.7
0.51
3.7
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.021
0.015
0.013
0.009
0.86
0.84
0.32
0.31
0.055
0.045
0.26
0.24
0.15
0.13
0.37
0.33
inches
0.19
0.020
0.15
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-10-02
95-01-19
SOT38-1
050G09
MO-001AE
1998 Jun 04
15
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1998 Jun 04
16
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2.0
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-01-14
95-02-04
SOT338-1
MO-150AC
1998 Jun 04
17
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-07-12
95-04-04
SOT403-1
MO-153
1998 Jun 04
18
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
SOLDERING
Introduction
SO, SSOP and TSSOP
REFLOW SOLDERING
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
DIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
WAVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
1998 Jun 04
19
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Even with these conditions:
REPAIRING SOLDERED JOINTS
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jun 04
20
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