74HCT595PW-T [NXP]
IC HCT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16, Shift Register;
| 型号： | 74HCT595PW-T |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16, Shift Register 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总28页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out
shift register with output latches;
3-state
Product specification
2003 Jun 25
Supersedes data of 1998 Jun 04
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
FEATURES
DESCRIPTION
• 8-bit serial input
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• 100 MHz (typical) shift out frequency
The 74HC/HCT595 is an 8-stage serial shift register with a
storage register and 3-state outputs. The shift register and
storage register have separate clocks.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Data is shifted on the positive-going transitions of the
SH_CP input. The data in each register is transferred to
the storage register on a positive-going transition of the
ST_CP input. If both clocks are connected together, the
shift register will always be one clock pulse ahead of the
storage register.
APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register.
The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided
with asynchronous reset (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state
bus driver outputs. Data in the storage register appears at
the output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
74HC
74HCT
tPHL/tPLH propagation delay
SH_CP to Q7’
CL = 50 pF; VCC = 4.5 V
19
25
ns
SH_CP to Qn
20
24
ns
MR to Q7’
100
100
3.5
115
52
ns
fmax
CI
maximum clock frequency SH_CP and ST_CP
57
MHz
pF
input capacitance
3.5
130
CPD
power dissipation capacitance per package
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. For 74HC595 the condition is VI = GND to VCC
.
For 74HCT595 the condition is VI = GND to VCC − 1.5 V.
2003 Jun 25
2
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
FUNCTION TABLE
See note 1.
INPUT
OE
OUTPUT
FUNCTION
SH_CP ST_CP
MR
DS
Q7’
Qn
X
X
X
X
↑
L
L
L
L
L
X
X
X
L
L
L
n.c.
L
a LOW level on MR only affects the shift registers
empty shift register loaded into storage register
X
H
Z
shift register clear; parallel outputs in high-impedance
OFF-state
↑
X
L
H
H
Q6’
n.c.
logic high level shifted into shift register stage 0;
contents of all shift register stages shifted through, e.g.
previous state of stage 6 (internal Q6’) appears on the
serial output (Q7’)
X
↑
↑
L
L
H
H
X
X
n.c.
Q6’
Qn’
Qn’
contents of shift register stages (internal Qn’) are
transferred to the storage register and parallel output
stages
↑
contents of shift register shifted through; previous
contents of the shift register is transferred to the
storage register and the parallel output stages
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH transition;
↓ = HIGH-to-LOW transition;
Z = high-impedance OFF-state;
n.c. = no change;
X = don’t care.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
PINS
PACKAGE
MATERIAL
CODE
RANGE
74HC595N
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
16
16
16
16
16
16
16
16
16
16
DIP16
DIP16
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
SOT38-4
SOT38-4
74HCT595N
74HC595D
SO16
SOT109-1
SOT109-1
SOT338-1
SOT338-1
SOT403-1
SOT403-1
SOT763-1
SOT763-1
74HCT595D
74HC595DB
74HCT595DB
74HC595PW
74HCT595PW
74HC595BQ
74HCT595BQ
SO16
SSOP16
SSOP16
TSSOP16
TSSOP16
DHVQFN16
DHVQFN16
2003 Jun 25
3
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
PINNING
PIN
SYMBOL
Q1
DESCRIPTION
1
2
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
ground (0 V)
Q2
3
Q3
4
Q4
5
Q5
6
Q6
7
Q7
8
GND
Q7’
9
serial data output
10
11
12
13
14
15
16
MR
master reset (active LOW)
shift register clock input
storage register clock input
output enable (active LOW)
serial data input
SH_CP
ST_CP
OE
DS
Q0
parallel data output
positive supply voltage
VCC
V
Q1
1
handbook, halfpage
CC
16
handbook, halfpage
1
2
3
4
5
6
7
8
16
15
Q1
Q2
V
CC
2
3
15
14
Q2
Q3
Q4
Q5
Q6
Q0
Q0
DS
Q3
14 DS
13 OE
4
5
6
7
13
12
11
10
OE
Q4
(1)
595
GND
ST_CP
Q5
12
11
ST_CP
SH_CP
MR
SH_CP
Q6
Q7
10 MR
Q7'
Q7
GND
9
8
9
MLA001
GND
Q7'
Top view
MBL893
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration DIP16, SO16 and
(T)SSOP16.
Fig.2 Pin configuration DHVQFN16.
2003 Jun 25
4
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
handbook, halfpage
13
12
10
11
11
12
ST_CP
Q7'
Q0
handbook, halfpage
OE
EN3
C2
SH_CP
ST_CP
9
15
1
R
MR
SRG8
C1/
SH_CP
Q1
14
15
2
1D
2D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
3
DS
Q2
1
2
3
4
5
6
7
9
3
14
Q3
DS
4
Q4
5
Q5
6
Q6
7
Q7
MR
10
OE
13
MLA002
MSA698
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
14 DS
SH_CP
11
8-STAGE SHIFT REGISTER
8-BIT STORAGE REGISTER
10 MR
Q7'
9
ST_CP
12
15
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
3
13 OE
3-STATE OUTPUTS
4
5
6
7
MLA003
Fig.5 Functional diagram.
5
2003 Jun 25
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
STAGE 0
STAGES 1 to 6
STAGE 7
Q7'
DS
D
Q
D
Q
D
Q
FF0
FF7
CP
CP
R
R
SH_CP
MR
D
Q
D
Q
LATCH
CP
LATCH
CP
ST_CP
OE
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
MLA010
Fig.6 Logic diagram.
2003 Jun 25
6
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
SH_CP
DS
ST_CP
MR
OE
Q0
high-impedance OFF-state
Q1
Q6
Q7
Q7'
MLA005-1
Fig.6 Timing diagram.
2003 Jun 25
7
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
RECOMMENDED OPERATING CONDITIONS
74HC
TYP. MAX. MIN.
74HCT
UNIT
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
2.0
TYP. MAX.
VCC
VI
5.0
−
6.0
4.5
0
5.0
5.5
V
V
V
input voltage
0
VCC
VCC
−
VCC
VCC
VO
output voltage
0
−
0
−
Tamb
tr, tf
ambient temperature
input rise and fall time
−40
−
−
+125 −40
−
+125 °C
VCC = 2.0 V
−
1000
500
−
−
−
−
−
ns
ns
ns
VCC = 4.5 V
CC = 6.0 V
−
6.0
−
6.0
−
500
−
V
−
400
LIMITED VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
IIK
−0.5
−
+7.0
±20
±20
V
input diode current
VI < −0.5 V to VI > VCC + 0.5 V
VO < −0.5 V to VO > VCC + 0.5 V
VO = −0.5 V to VCC + 0.5 V
Q7’ standard output
mA
mA
IOK
IO
output diode current
−
output source or sink current
−
±25
±35
±70
mA
mA
mA
Qn bus driver outputs
−
I
CC, IGND VCC or GND current
−
Tstg
Ptot
storage temperature
power dissipation
−65
−
+150 °C
500 mW
Tamb = −40 to +125 °C; note 1
Note
1. For DIP16 packages: above 70 °C derate linearly with 12 mW/K.
For SO16 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
For TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K.
2003 Jun 25
8
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
DC CHARACTERISTICS
Type 74HC
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C; note 1
VIH
HIGH-level input
voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
1.2
−
−
−
V
V
V
V
V
V
3.15
4.2
−
2.4
3.2
0.8
2.1
2.8
VIL
LOW-level input
voltage
0.5
−
1.35
1.8
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
all outputs
IO = −20 µA
2.0
4.5
6.0
1.9
4.4
5.9
2.0
4.5
6.0
−
−
−
V
V
V
Q7’ standard output
IO = −4.0 mA
IO = −5.2 mA
Qn bus driver outputs
IO = −6.0 mA
IO = −7.8 mA
VI = VIH or VIL
all outputs
4.5
6.0
3.84
5.34
4.32
5.81
−
−
V
V
4.5
6.0
3.84
5.34
4.32
5.81
−
−
V
V
VOL
LOW-level output
voltage
IO = 20 µA
2.0
4.5
6.0
−
−
−
0
0
0
0.1
0.1
0.1
V
V
V
Q7’ standard output
IO = 4.0 mA
4.5
6.0
−
−
0.15
0.16
0.33
0.33
V
V
IO = 5.2 mA
Qn bus driver outputs
IO = 6.0 mA
4.5
6.0
6.0
6.0
−
−
−
−
0.16
0.16
−
0.33
0.33
±1.0
±5.0
V
V
IO = 7.8 mA
ILI
input leakage current
VI = VCC or GND
µA
µA
IOZ
3-state output
VI = VIH or VIL;
−
OFF-state current
VO = VCC or GND
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
6.0
−
−
80
µA
2003 Jun 25
9
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +125 °C
VIH
HIGH-level input
voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
3.15
4.2
−
VIL
LOW-level input
voltage
0.5
−
1.35
1.8
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
all outputs
IO = −20 µA
2.0
4.5
6.0
1.9
4.4
5.9
−
−
−
−
−
−
V
V
V
Q7’ standard output
IO = −4.0 mA
4.5
6.0
3.7
5.2
−
−
−
−
V
V
IO = −5.2 mA
Qn bus driver outputs
IO = −6.0 mA
4.5
6.0
3.7
5.2
−
−
−
−
V
V
IO = −7.8 mA
VOL
LOW-level output
voltage
VI = VIH or VIL
all outputs
IO = 20 µA
4.5
4.5
−
−
−
−
0.1
0.4
V
V
V
Q7’ standard output
IO = 4.0 mA
Qn bus driver outputs
IO = 6.0 mA
4.5
5.5
5.5
−
−
−
−
−
−
0.4
ILI
input leakage current
VI = VCC or GND
±1.0
±10.0
µA
µA
IOZ
3-state output
VI = VIH or VIL;
OFF-state current
VO = VCC or GND
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
−
−
160
µA
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Jun 25
10
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
Type 74HCT
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C; note 1
VIH
HIGH-level input
voltage
4.5 to 5.5 2.0
1.6
−
V
V
VIL
LOW-level input
voltage
4.5 to 5.5
−
1.2
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL
all outputs
IO = −20 µA
4.5
4.5
4.5
4.4
4.5
−
−
−
V
V
V
Q7’ standard output
IO = −4.0 mA
3.84
3.7
4.32
4.32
Qn bus driver outputs
IO = −6.0 mA
VOL
LOW-level output
voltage
VI = VIH or VIL
all outputs
IO = 20 µA
4.5
4.5
−
−
0
0.33
0.33
V
V
V
Q7’ standard output
IO = 4.0 mA
0.15
Qn bus driver outputs
IO = 6.0 mA
4.5
5.5
5.5
−
−
−
0.16
−
0.33
±1.0
±5.0
ILI
input leakage current
VI = VCC or GND
µA
µA
IOZ
3-state output
VI = VIH or VIL;
−
OFF-state current
VO = VCC or GND
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
−
−
−
80
µA
µA
∆ICC
additional supply
current per input
VI = VCC − 2.1 V;
IO = 0; note 2
4.5 to 5.5
100
450
2003 Jun 25
11
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +125 °C
VIH
VIL
HIGH-level input
voltage
4.5 to 5.5 2.0
−
−
−
V
V
LOW-level input
voltage
4.5 to 5.5
−
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL
all outputs
IO = −20 µA
4.5
4.5
4.5
4.4
3.7
3.7
−
−
−
−
−
−
V
V
V
Q7’ standard output
IO = −4.0 mA
Qn bus driver outputs
IO = −6.0 mA
VOL
LOW-level output
voltage
VI = VIH or VIL
all outputs
IO = 20 µA
4.5
4.5
−
−
−
−
0.1
0.4
V
V
V
Q7’ standard output
IO = 4.0 mA
Qn bus driver outputs
IO = 6.0 mA
4.5
5.5
5.5
−
−
−
−
−
−
0.4
ILI
input leakage current
VI = VCC or GND
±1.0
±10.0
µA
µA
IOZ
3-state output
VI = VIH or VIL;
OFF-state current
VO = VCC or GND
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
−
−
−
−
160
490
µA
µA
∆ICC
additional supply
current per input
VI = VCC − 2.1 V;
IO = 0; note 2
4.5 to 5.5
Notes
1. All typical values are measured at Tamb = 25 °C.
2. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input,
multiply this value by the unit load coefficient per input pin:
a. pin DS: 0.25
b. pins MR, SH_CP, ST_CP and OE: 1.50.
2003 Jun 25
12
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
AC CHARACTERISTICS
Family 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = 25 °C
tPHL/tPLH
propagation delay
SH_CP to Q7’
see Fig.7
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
52
160
ns
19
15
55
20
16
47
17
14
47
17
14
41
15
12
17
6
32
27
175
35
30
175
35
30
150
30
26
150
30
26
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
propagation delay
ST_CP to Qn
see Fig.8
tPHL
propagation delay
MR to Q7’
see Fig.10
tPZH/tPZL
3-state output enable time see Fig.11
OE to Qn
tPHZ/tPLZ
3-state output disable time see Fig.11
OE to Qn
tW
shift clock pulse width
HIGH or LOW
see Fig.7
see Fig.8
see Fig.10
see Fig.9
see Fig.8
see Fig.9
75
15
13
75
15
13
75
15
13
50
10
9.0
75
15
13
+3
+3
+3
−
5
−
storage clock pulse width
HIGH or LOW
11
4
−
−
3
−
master reset pulse width
LOW
17
6.0
5.0
11
4.0
3.0
22
8
−
−
−
tsu
set-up time DS to SH_CP
−
−
−
set-up time
SH_CP to ST_CP
−
−
7
−
th
hold time DS to SH_CP
−6
−2
−2
−
−
−
2003 Jun 25
13
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
TEST CONDITIONS
WAVEFORMS CC (V)
removal time MR to SH_CP see Fig.10
SYMBOL
trem
PARAMETER
MIN.
+50
TYP.
−19
MAX.
UNIT
ns
V
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
+10
+9
9
−7
ns
−6
ns
fmax
maximum clock
pulse frequency
SH_CP or ST_CP
see Figs 7 and 8
30
91
108
MHz
MHz
MHz
30
35
Tamb = −40 to +85 °C
tPHL/tPLH
propagation delay
SH_CP to Q7’
see Fig.7
see Fig.8
see Fig.10
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
200
40
34
220
44
37
220
44
37
190
38
33
190
38
33
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
propagation delay
ST_CP to An
−
−
−
tPHL
propagation delay
MR to Q7’
−
−
−
t
t
PZH/tPZL
3-state output enable time see Fig.11
OE to Qn
−
−
−
PHZ/tPLZ
3-state output disable time see Fig.11
OE to Qn
−
−
−
tW
shift clock pulse width
HIGH or LOW
see Fig.7
see Fig.8
see Fig.10
see Fig.9
see Fig.8
95
19
16
95
19
16
95
19
16
65
13
11
95
19
16
−
−
storage clock pulse width
HIGH or LOW
−
−
−
master reset pulse width
LOW
−
−
−
tsu
set-up time DS to SH_CP
−
−
−
set-up time
SH_CP to ST_CP
−
−
−
2003 Jun 25
14
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
TEST CONDITIONS
WAVEFORMS
CC (V)
see Fig.9
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
ns
V
th
hold time DS to SH_CP
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
3
3
3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
trem
removal time MR to SH_CP see Fig.10
65
13
11
4.8
24
28
ns
ns
ns
fmax
maximum clock
pulse frequency
SH_CP or ST_CP
see Figs 7 and 8
MHz
MHz
MHz
T
amb = −40 to +125 °C
tPHL/tPLH
propagation delay
SH_CP to Q7’
see Fig.7
see Fig.8
see Fig.10
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
240
48
41
265
53
45
265
53
45
225
45
38
225
45
38
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
propagation delay
ST_CP to Qn
−
−
−
tPHL
propagation delay
MR to Q7’
−
−
−
t
t
PZH/tPZL
3-state output enable time see Fig.11
OE to Qn
−
−
−
PHZ/tPLZ
3-state output disable time see Fig.11
OE to Qn
−
−
−
tW
shift clock pulse width
HIGH or LOW
see Fig.7
see Fig.8
see Fig.10
110
22
19
110
22
19
110
22
19
−
−
storage clock pulse width
HIGH or LOW
−
−
−
master reset pulse width
LOW
−
−
−
2003 Jun 25
15
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
TEST CONDITIONS
WAVEFORMS CC (V)
see Fig.9
SYMBOL
tsu
PARAMETER
MIN.
75
TYP.
MAX.
UNIT
ns
V
set-up time DS to SH_CP
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
15
13
110
22
19
3
ns
ns
set-up time
SH_CP to ST_CP
see Fig.8
see Fig.9
ns
ns
ns
th
hold time DS to SH_CP
ns
3
ns
3
ns
trem
removal time MR to SH_CP see Fig.10
75
15
13
4
ns
ns
ns
fmax
maximum clock
pulse frequency
SH_CP or ST_CP
see Figs 7 and 8
MHz
MHz
MHz
20
24
2003 Jun 25
16
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
Family 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = 25 °C
tPHL/tPLH
propagation delay
SH_CP to Q7’
see Fig.7
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
−
−
−
−
−
25
42
ns
propagation delay
ST_CP to Qn
see Fig.8
24
23
21
18
6
40
40
35
30
−
ns
ns
ns
ns
ns
ns
ns
tPHL
propagation delay
MR to Q7’
see Fig.10
t
PZH/tPZL
PHZ/tPLZ
3-state output enable time see Fig.11
OE to Qn
t
3-state output disable time see Fig.11
OE to Qn
tW
shift clock pulse width
HIGH or LOW
see Fig.7
see Fig.8
see Fig.10
16
16
20
storage clock pulse width
HIGH or LOW
5
−
master reset pulse width
LOW
8
−
tsu
set-up time DS to SH_CP see Fig.9
4.5
4.5
16
16
5
8
−
−
ns
ns
set-up time
see Fig.8
SH_CP to ST_CP
th
hold time DS to SH_CP
see Fig.9
4.5
4.5
+3
−2
−7
−
−
ns
ns
trem
removal time
see Fig.10
+10
MR to SH_CP
fmax
maximum clock
pulse frequency
SH_CP or ST_CP
see Figs 7 and 8
4.5
30
52
−
MHz
Tamb = −40 to +85 °C
tPHL/tPLH
propagation delay
SH_CP to Q7’
see Fig.7
see Fig.8
see Fig.10
4.5
4.5
4.5
4.5
4.5
−
−
−
−
−
−
−
−
−
−
53
50
50
44
38
ns
ns
ns
ns
ns
propagation delay
ST_CP to Qn
tPHL
propagation delay
MR to Q7’
t
t
PZH/tPZL
PHZ/tPLZ
3-state output enable time see Fig.11
OE to Qn
3-state output disable time see Fig.11
OE to Qn
2003 Jun 25
17
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
TEST CONDITIONS
WAVEFORMS CC (V)
see Fig.7
SYMBOL
tW
PARAMETER
MIN.
20
TYP.
MAX.
UNIT
ns
V
shift clock pulse width
HIGH or LOW
4.5
4.5
4.5
−
−
−
−
−
−
storage clock pulse width
HIGH or LOW
see Fig.8
20
25
ns
ns
master reset pulse width
LOW
see Fig.10
tsu
set-up time DS to SH_CP see Fig.9
4.5
4.5
20
20
−
−
−
−
ns
ns
set-up time
see Fig.8
SH_CP to ST_CP
th
hold time DS to SH_CP
see Fig.9
4.5
4.5
3
−
−
−
−
ns
ns
trem
removal time
see Fig.10
13
MR to SH_CP
fmax
maximum clock
pulse frequency
SH_CP or ST_CP
see Figs 7 and 8
4.5
24
−
−
MHz
Tamb = −40 to +125 °C
tPHL/tPLH
propagation delay
SH_CP to Q7’
see Fig.7
see Fig.8
see Fig.10
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
−
−
−
−
−
−
−
−
−
63
60
60
53
45
−
ns
ns
ns
ns
ns
ns
ns
ns
propagation delay
ST_CP to Qn
−
tPHL
propagation delay
MR to Q7’
−
t
t
PZH/tPZL
PHZ/tPLZ
3-state output enable time see Fig.11
OE to Qn
−
3-state output disable time see Fig.11
OE to Qn
−
tW
shift clock pulse width
HIGH or LOW
see Fig.7
see Fig.8
see Fig.10
24
24
30
storage clock pulse width
HIGH or LOW
−
master reset pulse width
LOW
−
tsu
set-up time DS to SH_CP see Fig.9
4.5
4.5
24
24
−
−
−
−
ns
ns
set-up time
see Fig.8
SH_CP to ST_CP
th
hold time DS to SH_CP
see Fig.9
4.5
4.5
3
−
−
−
−
ns
ns
trem
removal time
see Fig.10
15
MR to SH_CP
fmax
maximum clock
pulse frequency
SH_CP or ST_CP
see Figs 7 and 8
4.5
20
−
−
MHz
2003 Jun 25
18
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
AC WAVEFORMS
1/f
max
V
SH_CP input
M
t
t
W
t
PLH
PHL
90%
V
Q7' output
M
10%
t
t
THL
MSA699
TLH
74HC595: VM = 50%; VI = GND to VCC
.
74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (SH_CP) to output (Q7’) propagation delays, the shift clock pulse width and
maximum shift clock frequency.
V
t
SH_CP input
ST_CP input
M
1/f
max
su
V
M
t
t
W
t
PLH
PHL
V
Qn output
M
MSA700
74HC595: VM = 50%; VI = GND to VCC
.
74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the storage clock (ST_CP) to output (Qn) propagation delays, the storage clock
pulse width and the shift clock to storage clock set-up time.
2003 Jun 25
19
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
V
SH_CP input
M
t
t
su
su
t
t
h
h
DS input
V
M
Q7' output
V
M
MLB196
74HC595: VM = 50%; VI = GND to VCC
.
74HCT595: VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.9 Waveforms showing the data set-up and hold times for the DS input.
V
MR input
SH_CP input
Q7' output
M
t
t
rem
W
V
M
t
PHL
V
M
MLB197
74HC595: VM = 50%; VI = GND to VCC
.
74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the Master Reset (MR) pulse width, the master reset to output (Q7’) propagation
delay and the master reset to shift clock (SH_CP) removal time.
2003 Jun 25
20
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
t
t
r
f
90%
V
OE input
M
10%
t
t
PZL
PLZ
Qn output
V
LOW-to-OFF
OFF-to-LOW
M
10%
t
t
PHZ
PZH
90%
Qn output
V
HIGH-to-OFF
OFF-to-HIGH
M
outputs
enabled
outputs
enabled
outputs
disabled
MSA697
74HC595: VM = 50%; VI = GND to VCC
.
74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the 3-state enable and disable times for input OE.
V
V
CC
CC
V
V
R
= 1 kΩ
I
O
L
PULSE
GENERATOR
D.U.T
R
C
50 pF
T
L
MGK563
TEST
SWITCH
open
tPLH/tPHL
Definitions for test circuit:
RL = Load resistor.
t
PLZ/tPZL
VCC
CL = Load capacitance including jig and probe capacitance.
tPHZ/tPZH
GND
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.12 Test circuit for 3-state outputs.
2003 Jun 25
21
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
2003 Jun 25
22
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
2003 Jun 25
23
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
2003 Jun 25
24
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
2003 Jun 25
25
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
2003 Jun 25
26
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jun 25
27
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/04/pp28
Date of release: 2003 Jun 25
Document order number: 9397 750 11263
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