74HCT597D,652 [NXP]
74HC(T)597 - 8-bit shift register with input flip-flops SOP 16-Pin;型号: | 74HCT597D,652 |
厂家: | NXP |
描述: | 74HC(T)597 - 8-bit shift register with input flip-flops SOP 16-Pin PC 光电二极管 逻辑集成电路 触发器 |
文件: | 总23页 (文件大小:217K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC597; 74HCT597
8-bit shift register with input flip-flops
Rev. 3 — 15 April 2014
Product data sheet
1. General description
The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an
8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage
register and the shift register have positive edge-triggered clocks. The shift register also
has direct load (from storage) and clear inputs. Inputs include clamp diodes that enable
the use of current limiting resistors to interface inputs to voltages in excess of VCC
.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC597: CMOS level
For 74HCT597: TTL level
8-bit parallel storage register inputs
Shift register has direct overriding load and clear
ESD protection:
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC5974N
74HCT597N
74HC597D
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
SO16
plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
SOT338-1
SOT403-1
74HCT597D
74HC597DB
74HCT597DB
74HC597PW
SSOP16
TSSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
4. Functional diagram
67&3
ꢃꢄ
05
ꢃꢂ
'6
ꢃꢆ
67&3
ꢃꢄ
05
ꢃꢂ
'6
ꢃꢆ
ꢃꢇ
ꢃ
'ꢂ
'ꢃ
'ꢄ
'ꢅ
'ꢆ
'ꢇ
'ꢈ
'ꢉ
'ꢂ
'ꢃ
'ꢄ
'ꢅ
'ꢆ
'ꢇ
'ꢈ
'ꢉ
ꢃꢇ
ꢃ
ꢄ
ꢄ
ꢅ
ꢀꢁ%,7
,1387
)/,3ꢁ)/236
6+,)7
ꢅ
,1387
)/,3ꢁ
)/236
ꢀꢁ%,7
ꢆ
5(*,67(5
6+,)7
ꢆ
ꢇ
5(*,67(5
ꢇ
ꢈ
ꢈ
ꢉ
ꢊ
4
ꢉ
ꢊ
4
ꢃꢅ
ꢃꢃ
ꢃꢅ
ꢃꢃ
3/ 6+&3
3/ 6+&3
DDDꢀꢁꢂꢃꢁꢄꢅ
DDDꢀꢁꢂꢃꢁꢄꢆ
Fig 1. Functional diagram
Fig 2. Logic symbol
65*ꢀ
5
ꢃꢂ
ꢃꢃ
ꢃꢅ
ꢃꢄ
&ꢅꢋ
&ꢄ
&ꢃ
ꢃ
ꢅ'
ꢄ'
ꢄ'
ꢃꢆ
ꢃꢇ
ꢃ
ꢃ'
ꢃ'
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢊ
ꢉ
DDDꢀꢁꢂꢃꢁꢄꢄ
Fig 3. IEC Logic symbol
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
2 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
05
6+&3
3/
67&3
'6
'ꢂ
&ꢄ
6
ꢃ'
ꢄ'
&ꢃ
5
&ꢅ ꢅ6
ꢅ5
ꢃ'
'ꢃ
'ꢄ
'ꢅ
'ꢆ
'ꢇ
'ꢈ
'ꢉ
6
&ꢃ
5
&ꢅ ꢅ6
ꢅ5
ꢃ'
6
&ꢃ
5
&ꢅ ꢅ6
ꢃ'
6
ꢅ5
&ꢃ
5
&ꢅ
6
ꢅ6
ꢅ5
ꢃ'
&ꢃ
5
ꢅ6
ꢅ5
&ꢅ
6
ꢃ'
&ꢃ
5
&ꢅ ꢅ6
ꢅ5
ꢃ'
6
&ꢃ
5
&ꢅ ꢅ6
ꢅ5
ꢃ'
6
4
&ꢃ
5
DDDꢀꢁꢂꢃꢁꢄꢇ
Fig 4. Logic diagram
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
3 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
5. Pinning information
5.1 Pinning
ꢀꢁ+&ꢂꢃꢀ
ꢀꢁ+&7ꢂꢃꢀ
ꢃꢈ
ꢃꢇ
ꢃꢆ
ꢃꢅ
ꢃꢄ
ꢃꢃ
ꢃꢂ
ꢊ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
'ꢃ
'ꢄ
9
&&
ꢀꢁ+&ꢂꢃꢀ
ꢀꢁ+&7ꢂꢃꢀ
'ꢂ
'ꢅ
'6
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢃꢈ
ꢃꢇ
ꢃꢆ
ꢃꢅ
ꢃꢄ
ꢃꢃ
ꢃꢂ
ꢊ
'ꢃ
'ꢄ
9
&&
'ꢂ
'ꢆ
3/
'ꢅ
'6
'ꢇ
67&3
6+&3
05
4
'ꢆ
3/
'ꢇ
67&3
6+&3
05
4
'ꢈ
'ꢈ
'ꢉ
'ꢉ
*1'
*1'
DDDꢀꢁꢂꢃꢁꢄꢈ
DDDꢀꢁꢂꢃꢁꢄꢉ
Fig 5. Pin configuration DIP16 and SO16
Fig 6. Pin configuration SSOP16 and TSSOP16
5.2 Pin description
Table 2.
Symbol
GND
Q
Pin description
Pin
8
Description
ground (0 V)
9
serial data output
MR
10
11
12
13
14
asynchronous master reset input (active LOW)
shift register clock input (LOW-to-HIGH, edge-triggered)
storage register clock input (LOW-to-HIGH, edge-triggered)
parallel load input (active LOW)
SHCP
STCP
PL
DS
serial data input
D0, D1, D2, D3, 15, 1, 2, 3, 4, 5, 6, 7
D4, D5, D6, D7
parallel data inputs
VCC
16
supply voltage
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
4 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
6. Functional description
Table 3.
Inputs
STCP
Function table[1]
Function
SHCP
PL
X
L
MR
X
X
X
data loaded to input latches
H
data loaded from inputs to shift register
data transferred from input flip-flops to shift register
no clock edge
X
X
X
L
H
L
L
invalid logic, state of shift register is indeterminate
when signals removed
X
X
X
H
H
L
shift register cleared
H
shift register clocked Qn = Qn1, Q0 = DS
[1] H = HIGH voltage level.
L = LOW voltage level.
X = don’t care.
= positive-going transition.
6+&3
'6
05
3/
67&3
'ꢂ
'ꢃ
'ꢄ
'ꢅ
/
/
/
/
/
/
/
/
/
/
/
+
+
/
/
+
/
+
/
'ꢆ
'ꢇ
'ꢈ
+
+
/
'ꢉ
4
+
/
+
/
+
/
+
+
/
+
/
+
/
+
/
/
/
/
/
+
+
UHVHW
VKLIW
UHJLVWHU
VHULDOꢌVKLIW
VHULDOꢌVKLIW
VHULDOꢌVKLIW
VHULDOꢌVKLIW
ORDGꢌLQSXW
UHJLVWHU
ORDGꢌLQSXW
UHJLVWHU
SDUDOOHOꢌORDG
VKLIWꢌUHJLVWHU
SDUDOOHOꢌORDG
VKLIWꢌUHJLVWHU
SDUDOOHOꢌORDGꢌERWK
LQSXWꢌDQGꢌVKLIWꢌUHJLVWHUV
DDDꢀꢁꢂꢃꢁꢄꢊ
Fig 7. Timing diagram
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
5 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
25
+50
-
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
storage temperature
total power dissipation
65
+150
750
500
[1]
[2]
DIP16 package
-
-
mW
mW
SO16, SSOP16 and TSSOP16 packages
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC597
74HCT597
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
+25
40
+25
C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
6 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
74HC597
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1.0
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
8.0
-
A
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
-
-
80.0
-
-
-
160.0 A
input
3.5
-
pF
capacitance
74HCT597
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 4.0 mA
0.15 0.26
0.1
0.33
1.0
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
1.0
A
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
7 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
Max
Min
Max
Min
Max
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80.0
-
160.0 A
ICC
additional
VI = VCC 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; DS input
per input pin; Dn inputs
-
-
-
25
30
90
-
-
-
112.5
135
-
-
-
122.5 A
108
540
147
735
A
A
per input pin; PL, MR
inputs
150
675
per input pin; STCP,
SHCP inputs
-
-
150
3.5
540
-
-
-
675
-
-
-
735
-
A
CI
input
pF
capacitance
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
Symbol Parameter Conditions
74HC597
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ Max Min
Max
Min
Max
[1]
tpd
propagation SHCP to Q; see Figure 8
delay
VCC = 2.0 V
-
-
-
-
55
20
17
16
175
35
-
-
-
-
-
220
44
-
-
-
-
-
265
53
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
30
37
45
[1]
[1]
MR to Q; see Figure 9
VCC = 2.0 V
-
-
-
58
21
17
175
35
-
-
-
220
44
-
-
-
265
53
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
30
37
45
STCP to Q; see Figure 8
VCC = 2.0 V
-
-
-
-
80
29
25
23
250
50
-
-
-
-
-
315
63
-
-
-
-
-
375
75
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
43
54
64
[1]
PL to Q; see Figure 10
VCC = 2.0 V
-
-
-
-
69
25
21
20
215
43
-
-
-
-
-
270
54
-
-
-
-
-
325
65
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
37
46
55
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
8 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Typ Max Min
Min
Max
Min
Max
[2]
tt
transition
time
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
6
19
tW
pulse width STCP HIGH or LOW;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
11
4
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
3
17
20
SHCP HIGH or LOW;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
4
17
20
MR LOW; see Figure 9
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
V
CC = 6.0 V
6
17
20
PL LOW; see Figure 10
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
17
20
trec
recovery
time
MR to SHCP; see
Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
60
12
10
3
1
1
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
9 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Typ Max Min
Min
Max
Min
Max
tsu
set-up time Dn to STCP; see
Figure 12
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
60
12
10
8
3
2
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
DS to SHCP; see
Figure 12
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
60
12
10
11
4
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
3
PL to SHCP; see
Figure 13
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
60
12
10
11
4
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
3
th
hold time
Dn to STCP; see
Figure 12
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
5
5
5
3
1
1
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
PL, DS to SHCP; see
Figure 12
VCC = 2.0 V
VCC = 4.5 V
5
5
5
6
2
2
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 6.0 V
fmax
maximum
frequency
SHCP; see Figure 8
VCC = 2.0 V
6.0
30
-
29
87
-
-
-
-
-
4.8
24
-
-
-
-
-
-
4.0
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
96
35
-
104
29
28
-
24
-
[3]
CPD
power
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
dissipation
capacitance
74HC_HCT597
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74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ Max Min
Max
Min
Max
74HCT597
[1]
tpd
propagation SHCP to Q; see Figure 8
delay
VCC = 4.5 V
-
-
23
20
40
-
-
-
50
-
-
-
60
-
ns
ns
VCC = 5.0 V; CL = 15 pF
MR to Q; see Figure 9
VCC = 4.5 V
[1]
[1]
-
28
49
-
61
-
74
ns
STCP to Q; see Figure 8
VCC = 4.5 V
-
-
33
29
57
-
-
-
71
-
-
-
86
-
ns
ns
VCC = 5.0 V; CL = 15 pF
PL to Q; see Figure 10
VCC = 4.5 V
[1]
[2]
-
-
30
26
52
-
-
-
65
-
-
-
78
-
ns
ns
VCC = 5.0 V; CL = 15 pF
see Figure 8
tt
transition
time
VCC = 4.5 V
-
7
6
15
-
-
19
-
-
22
-
ns
ns
tW
pulse width STCP HIGH or LOW;
see Figure 8
VCC = 4.5 V
16
20
24
SHCP HIGH or LOW;
see Figure 8
VCC = 4.5 V
16
25
20
7
-
-
-
20
31
25
-
-
-
24
38
30
-
-
-
ns
ns
ns
MR LOW; see Figure 9
VCC = 4.5 V
14
10
PL LOW; see Figure 10
VCC = 4.5 V
trec
recovery
time
MR to SHCP; see
Figure 11
VCC = 4.5 V
12
12
12
12
2
5
-
-
-
-
15
15
15
15
-
-
-
-
18
18
18
18
-
-
-
-
ns
ns
ns
ns
tsu
set-up time Dn to STCP; see
Figure 12
VCC = 4.5 V
DS to SHCP; see
Figure 12
VCC = 4.5 V
2
PL to SHCP; see
Figure 13
VCC = 4.5 V
4
74HC_HCT597
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Product data sheet
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74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Typ Max Min
Min
Max
Min
Max
th
hold time
Dn to STCP; see
Figure 12
VCC = 4.5 V
5
1
2
-
-
5
5
-
-
5
-
-
ns
ns
PL, DS to SHCP; see
Figure 12
VCC = 4.5 V
5
5
fmax
maximum
frequency
SHCP; see Figure 8
VCC = 4.5 V
30
-
75
83
32
-
-
-
24
-
-
-
-
20
-
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
[3]
CPD
power
CL = 50 pF; f = 1 MHz;
-
-
-
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] tpd is the same as tPLH and tPHL
[2] tt is the same as tTHL and tTLH
.
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
ꢃꢋI
PD[
9
,
67&3ꢍꢌ6+&3
LQSXW
9
0
*1'
W
:
W
W
3+/
3/+
9
2+
4ꢌRXWSXW
9
0
9
2/
DDDꢀꢁꢂꢃꢈꢆꢇ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Shift clock and storage clock inputs to output, propagation delays, pulse widths and maximum clock
frequency
74HC_HCT597
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Product data sheet
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12 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
9
,
9
05ꢌLQSXW
4ꢌRXWSXW
0
*1'
W
:
W
3+/
9
2+
9
0
9
2/
DDDꢀꢁꢂꢃꢈꢆꢊ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. input (MR) to (Q), output propagation delays and (MR) pulse width
ꢃꢋI
PD[
9
,
9
3/ꢌLQSXW
4ꢌRXWSXW
0
*1'
W
:
W
W
3/+
3+/
9
2+
ꢊꢂꢌꢎ
ꢊꢂꢌꢎ
9
0
ꢃꢂꢌꢎ
ꢃꢂꢌꢎ
9
2/
W
W
7/+
7+/
DDDꢀꢁꢂꢃꢈꢅꢂ
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 10. Input (PL) to (Q), output propagation delays, PL pulse width and output transition times
9
,
9
05ꢌLQSXW
0
*1'
W
UHF
9
,
6+&3ꢌLQSXW
9
0
*1'
DDDꢀꢁꢂꢃꢈꢅꢃ
Measurement points are given in Table 8.
Fig 11. Input (MR) to shift clock (SHCP) and storage clock (STCP) recovery times
74HC_HCT597
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Product data sheet
Rev. 3 — 15 April 2014
13 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
9
,
SRVLWLYH
9
9
0
0
'6ꢍꢌ'QꢌLQSXW
*1'
9
,
QHJDWLYH
'6ꢍꢌ'QꢌLQSXW
*1'
W
W
K
VX
9
,
9
9
0
0
6+&3ꢌLQSXW
67&3ꢌLQSXW
*1'
9
,
*1'
W
W
K
VX
DDDꢀꢁꢂꢃꢈꢅꢉ
Measurement points are given in Table 8.
Fig 12. Hold and set-up times for (DS), (Dn) inputs to (SHCP), (STCP) inputs
9
,
3/ꢌLQSXW
9
0
*1'
9
,
9
0
6+&3ꢌLQSXW
*1'
W
W
K
VX
DDDꢀꢁꢂꢃꢈꢅꢄ
Measurement points are given in Table 8.
Fig 13. Set-up times for (PL) input to (SHCP) input
Table 8.
Type
Measurement points
Input
VM
Output
VI
VM
74HC597
0.5 VCC
1.3 V
GND to VCC
GND to 3 V
0.5 VCC
1.3 V
74HCT597
74HC_HCT597
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Product data sheet
Rev. 3 — 15 April 2014
14 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 14. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC597
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT597
open
GND
VCC
74HC_HCT597
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Product data sheet
Rev. 3 — 15 April 2014
15 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
12. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 15. Package outline SOT38-4 (DIP16)
74HC_HCT597
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Product data sheet
Rev. 3 — 15 April 2014
16 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 16. Package outline SOT109-1 (SO16)
74HC_HCT597
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Product data sheet
Rev. 3 — 15 April 2014
17 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 17. Package outline SOT338-1 (SSOP16)
74HC_HCT597
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Product data sheet
Rev. 3 — 15 April 2014
18 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 18. Package outline SOT403-1 (TSSOP16)
74HC_HCT597
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Product data sheet
Rev. 3 — 15 April 2014
19 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20140415
Data sheet status
Change notice
Supersedes
74HC_HCT597 v.3
Modifications:
Product data sheet
-
74HC_HCT597_CNV v.2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT597_CNV v.2
19901201
Product specification
-
-
74HC_HCT597
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Product data sheet
Rev. 3 — 15 April 2014
20 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
21 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
22 of 23
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 April 2014
Document identifier: 74HC_HCT597
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