74HCT648PW-T [NXP]
IC HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, Bus Driver/Transceiver;
| 型号： | 74HCT648PW-T |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, Bus Driver/Transceiver 总线收发器 |
| 文件： | 总12页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT648
Octal bus transceiver/register;
3-state; inverting
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
bus will be clocked into the registers as the appropriate
clock (CPAB and CPBA) goes to a HIGH logic level. Output
enable (OE) and direction (DIR) inputs are provided to
control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source
inputs (SAB and SBA) can multiplex stored and real-time
(transparent mode) data. The direction (DIR) input
determines which bus will receive data when OE is active
(LOW). In the isolation mode (OE = HIGH), “A” data may
be stored in the “B” register and/or “B” data may be stored
in the “A” register.
FEATURES
• Independent register for A and B buses
• Multiplexed real-time and stored data
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT648 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
When an output function is disabled, the input function is
still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.
The 74HC/HCT648 consist of bus transceiver circuits with
3-state inverting outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data
directly from the internal registers. Data on the “A” or “B”
The “648” is functionally identical to the “646”, but has
inverting data paths.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
fmax
propagation delay An, Bn to Bn, An
maximum clock frequency
input capacitance
11
11
ns
CL = 15 pF; VCC = 5 V
75
3.5
88
3.5
MHz
pF
CI
power dissipation capacitance per
channel
CPD
notes 1 and 2
30
31
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi +∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
PIN DESCRIPTION
PIN NO.
SYMBOL
CPAB
SAB
NAME AND FUNCTION
1
A to B clock input (LOW-to-HIGH, edge-triggered)
select A to B source input
2
3
DIR
direction control input
4, 5, 6, 7, 8, 9, 10, 11
A0 to A7
GND
B0 to B7
OE
A data inputs/outputs
12
ground (0 V)
20, 19, 18, 17, 16, 15, 14, 13
B data inputs/outputs
21
22
23
24
output enable input (active LOW)
select B to A source input
SBA
CPBA
VCC
B to A clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS (1)
DATA I/O (2)
A0 TO A7 B0 TO B7
FUNCTION
OE
DIR
CPAB
CPBA
SAB
SBA
H
H
X
X
H or L
↑
H or L
↑
X
X
X
X
isolation
store A and B data
input
output
input
input
input
output
L
L
L
L
X
X
X
X
X
L
H
real-time B data to A bus
stored B data to A bus
H or L
L
L
H
H
X
X
X
L
H
X
X
real-time A data to B bus
stored A data to B bus
H or L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH level transition
2. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
December 1990
4
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
t
PHL/ tPLH propagation delay
An, Bn to Bn, An
39
14
11
135
27
23
170
34
29
205
41
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
CPAB, CPBA to Bn, An
74
27
22
230
46
39
290
58
49
345
69
59
2.0
4.5
6.0
Fig.7
t
t
PHL/ tPLH propagation delay
AB, SBA to Bn, An
55
20
16
190
38
32
240
48
41
285
57
48
2.0
4.5
6.0
Fig.8
S
PZH/ tPZL 3-state output enable
time OE to An, Bn
52
19
15
175
35
30
220
44
37
265
53
45
2.0
4.5
6.0
Fig.9
tPHZ/ tPLZ 3-state output disable
time OE to An, Bn
61
22
18
175
35
30
220
44
37
265
53
45
2.0
4.5
6.0
Fig.9
t
PZH/ tPZL 3-state output enable
time DIR to An, Bn
52
19
15
175
35
30
220
44
37
265
53
45
2.0
4.5
6.0
Fig.10
Fig.10
Fig.6 and Fig.8
Fig.7
tPHZ/ tPLZ 3-state output disable
time DIR to An, Bn
55
20
16
175
35
30
220
44
37
265
53
45
2.0
4.5
6.0
t
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
2.0
4.5
6.0
tW
clock pulse width
HIGH or LOW
CPAB or CPBA
80
16
14
25
9
7
100
20
17
120
24
20
2.0
4.5
6.0
60
12
10
0
0
0
75
15
13
90
18
15
2.0
4.5
6.0
set-up time
An, Bn to CPAB, CPBA
tsu
ns
ns
Fig.7
Fig.7
Fig.7
35
7
6
6
2
2
45
9
8
55
11
9
2.0
4.5
6.0
hold time
An, Bn to CPAB, CPBA
th
6.0
30
35
22
68
81
4.8
24
28
4.0
20
24
2.0
MHz 4.5
6.0
maximum clock pulse
frequency
fmax
December 1990
6
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
SAB, SBA
A0 to A7; and B0 to B7;
0.60
0.75
INPUT
UNIT LOAD COEFFICIENT
CPAB; CPBA
OE
DIR
;
1.50
1.50
1.25
December 1990
7
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An, Bn to Bn, An
14
25
20
21
27
46
38
40
34
58
48
50
41
69
57
60
ns
ns
ns
ns
4.5
4.5
4.5
4.5
Fig.6
Fig.7
Fig.8
Fig.9
t
PHL/ tPLH propagation delay
CPAB, CPBA to Bn, An
t
PHL/ tPLH propagation delay
SAB, SBA to Bn, An
tPZH/ tPZL 3-state output enable
time
OE to An, Bn
t
PHZ/ tPLZ 3-state output disable
20
20
21
35
40
35
12
44
50
44
15
53
60
53
18
ns
ns
ns
4.5
4.5
4.5
Fig.9
time
OE to An, Bn
tPZH/ tPZL 3-state output enable
Fig.10
Fig.10
time
DIR to An, Bn
t
t
PHZ/ tPLZ 3-state output disable
time
DIR to An, Bn
THL/ tTLH output transition time
5
7
ns
ns
4.5
4.5
Fig.6 and Fig.8
Fig.7
tW
clock pulse width
HIGH or LOW
CPAB or CPBA
16
20
24
tsu
th
set-up time
An, Bn to CPAB, CPBA
12
5
2
15
5
18
5
ns
ns
ns
4.5
4.5
Fig.7
Fig.7
hold time
An, Bn to CPAB, CPBA
0
fmax
maximum clock pulse
frequency
30
80
24
20
MHz Fig.7
December 1990
8
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input An, Bn to output Bn, An propagation delays and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the An, Bn to CPAB, CPBA set-up and hold times, clock CPAB, CPBA pulse width,
maximum clock pulse frequency and the CPAB, CPBA to output Bn, An propagation delays.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the input SAB, SBA to output Bn, An propagation delays and output transition times.
December 1990
9
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the input OE to output An, Bn 3-state enable and disable times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the input DIR to output An, Bn 3-state enable and disable times.
December 1990
10
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
APPLICATION INFORMATION
Fig.11 Data storage from A and/or B bus.
Fig.12 Real-time transfer from bus A to bus B.
Fig.13 Real-time transfer from bus B to bus A.
11
December 1990
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
12
相关型号：
74HCT652NB
IC HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24, Bus Driver/Transceiver
NXP
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