74HCT652D,118 [NXP]
74HC(T)652 - Octal bus transceiver/register; 3-state SOP 24-Pin;
| 型号： | 74HCT652D,118 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)652 - Octal bus transceiver/register; 3-state SOP 24-Pin 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总10页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT652
Octal bus transceiver/register;
3-state
September 1993
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
compliance with Jedec standard
no. 7A.
possible and when OEBA is HIGH,
there is no data transmission from Bn
to An possible. When SAB and SBA are
in the real time transfer mode, it is
also possible to store data without
using the internal D-type flip-flops by
simultaneously enabling OEAB and
OEBA. In this configuration each
output reinforces its input. Thus when
all other data sources to the two sets
of bus lines are at high-impedance,
each set of the bus lines will remain at
its last state. This type differs from the
HC/HCT646 in one extra
bus-management function. This is the
possibility to transfer stored “A data to
the “B” bus and transfer stored ”B”
data to the ”A” bus at the same time.
The examples at the application
information demonstrate all bus
management functions.
FEATURES
• Multiplexed real-time and stored
data
The 74HC/HCT652 consist of 8
non-inverting bus transceiver circuits
with 3-state outputs, D-type flip-flops
and central circuitry arranged for
multiplexed transmission of data
directly from the data bus or from the
internal storage registers. Data on the
“A” or “B” or both buses, will be stored
in the internal registers, at the
• Independent register for A and B
buses
• Independent enables for A and B
buses
• 3-state
• Output capability: Bus driver
• Low power consumption by CMOS
technology
appropriate clock pins (CPAB or
CPBA) regardless of the select pins
(SAB and SBA) or output enable (OEAB
and OEBA) control pins. Depending
on the select inputs SAB and SBA data
can directly go from input to output
(real time mode) or data can be
controlled by the clock (storage
mode), this is when the output enable
pins this operating mode permits. The
output enable pins OEAB and OEBA
determine the operation mode of the
transceiver. When OEAB is LOW, no
data transmission from An to Bn is
• ICC category: MSI.
APPLICATIONS
• Bus interfaces.
DESCRIPTION
Schmitt-trigger action in the clock
inputs makes the circuit highly
tolerant to slower clock rise and fall
times.
The 74HC/HCT652 are high-speed
SI-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf = 6 ns; VCC = 4.5 V; CL = 50 pF.
TYPICAL
SYMBOL
PLH/tPZL
PARAMETER
CONDITIONS
UNIT
HC
HCT
t
propagation delay An/Bn to Bn /An
propagation delay CPAB/CPBA to Bn /An
propagation delay SAB/SBA to Bn /An
3-state output enable time OEAB/OEBA to Bn/An
3-state output disable time OEAB/OEBA to Bn/An
maximum clock frequency
CL = 15 pF;
VCC = 5 V
13
18
20
14
12
92
3.5
26
13
20
23
15
13
92
3.5
28
ns
ns
ns
tPHZ/tPZL
PHZ/tPLZ
ns
t
ns
fmax
CI
MHz
pF
pF
input capacitance
CPD
power dissipation capacitance per channel
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
∑ (CL × VCC2 × fo) = sum of the outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
September 1993
2
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
ORDERING AND PACKAGE INFORMATION
TYPE NUMBER
PACKAGE
MATERIAL
PINS
24
24
PIN POSITION
CODE
74HC/HCT652N
74HC/HCT652D
DIL
SO
plastic
plastic
SOT101L
SOT137A
PINNING
SYMBOL
PIN
DESCRIPTION
A to B clock input
CPAB
SAB
1
2
3
select A to B source input
output enable A to B input
A data inputs/outputs
ground (0 V)
OEAB
A0..A7
GND
B7..B0
OEBA
SBA
4..11
12
13..20
21
B data inputs/outputs
output enable B to A input
select B to A source input
B to A clock input
22
CPBA
VCC
23
24
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
FUNCTION TABLE
INPUTS (1)
DATA I/O (2)
OPERATION OR FUNCTION
HC/HCT652
OEAB OEBA CPAB CPBA SAB SBA
A1 THRU A8
B1 THRU B8
L
L
H
H
H
H
X
L
H or L H or L
X
X
X
L
X
X
X
X
X
L
Isolation
Input
Input
↑
↑
Store A and B data
X
H
L
↑
H or L
Input
Input
Not specified
Output
Store A, Hold B
↑
↑
Store A in both registers
Hold A, Store B
H or L
↑
X
X
X
X
L
Not specified
Ouput
Input
L
↑
X
↑
X
Input
Store B in both registers
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored B Data to A Bus
L
L
L
Ouput
Input
Input
Output
Output
L
L
X
H or L
X
H
X
X
H
H
H
H
X
H or L
X
H
H
L
H or L H or L
H
H
Output
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH transition
2. The data output functions may be enabled or disabled by various signals at OEAB and OEBA inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
Fig.4 Functional diagram.
September 1993
4
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
Fig.5 Logic diagram.
September 1993
5
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
tPHL/tPLH propagation delay
An, Bn to Bn, An
−
−
−
44
16
13
135
27
23
−
−
−
170
34
29
−
−
−
205
41
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
tPHL/tPLH propagation delay
CPAB, CPBA to Bn, An
−
−
−
61
22
18
190
38
32
−
−
−
240
48
41
−
−
−
285
57
48
2.0 Fig.7
4.5
6.0
t
PHL/tPLH propagation delay
AB, SBA to Bn, An
−
−
−
63
23
18
195
39
33
−
−
−
245
49
42
−
−
−
295
59
50
2.0 Fig.8
4.5
6.0
S
tPZH/tPZL
3-state output enable
time
−
−
−
47
17
14
150
30
26
−
−
−
190
38
33
−
−
−
225
45
38
2.0 Fig.9
4.5
6.0
OEAB, OEBA to An, Bn
t
t
PHZ/tPLZ
3-state output disable
time
OEAB, OEBA to An, Bn
−
−
−
41
15
12
150
30
26
−
−
−
190
38
33
−
−
−
225
45
38
2.0 Fig.9
4.5
6.0
THL/tTLH
output transition time
−
−
−
14
5
4
60
12
10
−
−
−
75
15
13
−
−
−
90
18
15
2.0 Figs 6, 8
4.5
6.0
tW
clock pulse width
HIGH or LOW
CPAB or CPBA
80
16
14
17
6
5
−
−
−
100
20
17
−
−
−
120
24
20
−
−
−
2.0 Fig.7
4.5
6.0
tsu
set-up time
100 17
20
17
−
−
−
125
25
21
−
−
−
150
30
26
−
−
−
2.0 Fig.7
4.5
6.0
An, Bn to CPAB, CPBA
6
5
th
hold time
25
5
4
−8
−3
−2
−
−
−
30
6
5
−
−
−
35
7
6
−
−
−
2.0 Fig.7
4.5
6.0
An, Bn to CPAB, CPBA
fmax
maximum clock pulse
frequency
6.0
30
35
16
83
98
−
−
−
4.8
24
28
−
−
−
4.0
20
24
−
−
−
MHz 2.0 Fig.7
4.5
6.0
September 1993
6
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI.
Note to the HCT types
The value of additional quiescent supply current (∆ICC) for unit a load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below
INPUT
SAB, SBA
UNIT LOAD COEFFICIENT
0.75
A0 to A7 and B0 to B7
CPAB, CPBA
OEAB
0.75
1.50
1.50
1.50
OEBA
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
−40 to +85 −40 to +125 UNIT
TEST CONDITIONS
INPUT
PARAMETER
+25
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC
WAVEFORMS
(V)
tPHL/tPLH propagation delay
An, Bn to Bn, An
−
−
−
−
16
23
27
18
27
39
46
33
−
−
−
−
34
49
55
41
−
−
−
−
41
59
66
50
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.7
4.5 Fig.8
4.5 Fig.9
t
t
t
PHL/tPLH propagation delay
CPAB, CPBA to Bn, An
PHL/tPLH propagation delay
SAB, SBA to Bn, An
PZH/tPZL 3-state output enable
time
OEAB, OEBA to An, Bn
t
PHZ/tPLZ 3-state output disable
time
−
16
35
−
44
−
53
ns
4.5 Fig.9
OEAB, OEBA to An, Bn
tTHL/tTLH output transition time
−
5
6
12
−
15
−
18
ns
ns
4.5 Fig.6, 8
4.5 Fig.7
tW
clock pulse width
HIGH or LOW
CPAB or CPBA
16
−
20
−
24
−
tsu
th
set-up time
An, Bn to CPAB, CPBA
10
5
5
−
−
−
13
6
−
−
−
15
8
−
−
−
ns
ns
4.5 Fig.7
4.5 Fig.7
hold time
An, Bn to CPAB, CPBA
−2
83
fmax
maximum clock pulse
frequency
30
24
20
MHz 4.5 Fig.7
September 1993
7
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the An, Bn to CPAB
,
CPBA set-up and hold times, clock CPAB
,
Fig.6 Waveforms showing the input An, Bn to
output Bn, An propagation delay times and
the output transition times.
CPBA pulse width, maximum clock pulse
frequency and the CPAB, CPBA to output Bn,
An propagation delays.
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the output enable
inputs (OEAB, OEBA) to outputs An, Bn
enable and disable times and the input
rise and fall times.
Fig.8 Waveforms showing the input SAB, SBA to
output Bn, An propagation delay times and
the output transition times.
September 1993
8
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
APPLICATION INFORMATION
Fig.10 Application information.
September 1993
9
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
10
相关型号：
74HCT652NB
IC HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24, Bus Driver/Transceiver
NXP
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