74HCT7403D,112 [NXP]
74HC(T)7403 - 4-Bit x 64-word FIFO register; 3-state SOP 16-Pin;
| 型号： | 74HCT7403D,112 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)7403 - 4-Bit x 64-word FIFO register; 3-state SOP 16-Pin 先进先出芯片 |
| 文件： | 总28页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7403
4-Bit x 64-word FIFO register;
3-state
September 1993
Product specification
Supersedes data of October 1990
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
FEATURES
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
• Synchronous or asynchronous
operation
TYP.
SYMBOL
PHL/tPLH
fmax
PARAMETER
CONDITIONS
UNIT
• 3-state outputs
HC HCT
• 30 MHz (typical) shift-in and
shift-out rates
t
propagation delay SO, CL = 15 pF;
SI to DIR and DOR
15
17
ns
VCC = 5 V
• Readily expandable in word and bit
dimensions
maximum clock
frequency
30
30
MHz
• Pinning arranged for easy board
layout: input pins directly opposite
output pins
CI
input capacitance
3.5
3.5
pF
pF
CPD
power dissipation
capacitance per
package
note 1
475
490
• Output capability: driver (8 mA)
• ICC category: LSI.
Note
1. For HC the condition is VI = GND to VCC
.
APPLICATIONS
For HCT the condition is VI = GND to VCC −1.5 V.
• High-speed disc or tape controller
• Communications buffer.
ORDERING INFORMATION
PACKAGE
EXTENDED
TYPE NUMBER
GENERAL DESCRIPTION
PINS
PIN POSITION
MATERIAL
CODE
The 74HC/HCT7403 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no.7A.
74HC/HCT7403N
74HC/HCT7403D
16
16
DIL
plastic
plastic
SOT38Z
SOT162
SO16L
The “7403” is an expandable, First-In
First-Out (FIFO) memory organized
as 64 words by 4 bits. A guaranteed
15 MHz data-rate makes it ideal for
high-speed applications. A higher
data-rate can be obtained in
applications where the status flags
are not used (burst-mode).
With separate controls for shift-in (SI)
and shift-out (SO), reading and
writing operations are completely
independent, allowing synchronous
and asynchronous data transfers.
Additional controls include a
master-reset input (MR), an output
enable input (OE) and flags. The
data-in-ready (DIR) and
data-out-ready (DOR) flags indicate
the status of the device.
September 1993
2
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
PINNING
SYMBOL
OE
PIN
DESCRIPTION
1
2
3
output enable input (active LOW)
data-in-ready output
DIR
handbook, halfpage
SI
shift-in input (active HIGH)
parallel data input
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
OE
DO to D3
4, 5,
6, 7
DIR
SO
SI
DOR
GND
MR
8
9
ground
asynchronous master-reset
input (active LOW)
D
0
Q
0
7403
D
1
Q
1
Q3 to Q0
10,11, data output
12, 13
D
2
Q
2
D
3
Q
3
DOR
SO
14
15
16
data-out-ready output
shift-out input (active LOW)
positive supply voltage
GND
MR
VCC
MGA672
Fig.1 Pin configuration.
handbook, halfpage
FIFO 64 x 4
1
handbook, halfpage
1
2
EN4
1Z2
[IR] 3
14
[OR] 6
OE
CTR
1 ( /C2)
D
D
D
D
Q
Q
Q
Q
4
5
6
7
13
12
11
10
0
1
2
3
0
1
2
3
3
9
<
G1
G5
CT 64
CT = 0
5
>
CT 0
15
5Z6
4
5
6
7
13
12
11
10
4
DOR
DIR
14
2
2D
3
SI
15
SO
MR
9
MGA674
MGA676
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
DOR
A
SI
DOR
SO
Q
DOR
B
B
B
DIR
SO
SO
A
B
SI
SI
7403
FIFO A
7403
nB
4
A
DATA OUTPUT
FIFO B
DIR
DIR
Q
4
D
nB
A
nA
DATA INPUT
4
D
nA
MR
OE
MR
OE
MR
OE
MGA679
Fig.4 Functional diagram.
FUNCTIONAL DESCRIPTION
Expanded format (see Fig.17)
Serial expansion
A DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D0 to D3 is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
The DOR and DIR signals are used to
allow the “7403” to be cascaded. Both
parallel and serial expansion is
possible.
Serial expansion is accomplished by:
• tying the data outputs of the first
device to the data inputs of the
second device
Serial expansion is only possible with
typical devices.
• connecting the DOR pin of the first
device to the SI pin of the second
device
Parallel expansion
• connecting the SO pin of the first
device to the DIR pin of the second
device.
Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
A DOR flag indicates the output stage
status, either data available (DOR =
HIGH) or busy (DOR = LOW). When
SO and DOR are HIGH, data is
available at the outputs (Q0 to Q3).
When SO is set LOW new data may
be shifted into the output stage, once
complete DOR is set HIGH.
September 1993
4
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
SM1B8
u
September 1993
5
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that VOH and VOL are not
valid for driver output.
They are replaced by the values given below.
Output capability: driver 8 mA
ICC category: LSI.
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HC
Tamb (°C)
TEST CONDITION
SYMBOL
PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
(V)
VI
OTHER
MIN TYP MAX MIN MAX MIN MAX
VOH
HIGH level
output voltage
all outputs
1.9
4.4
5.9
2.0
4.5
6
−
−
−
1.9
4.4
5.9
−
−
−
1.9
4.4
5.9
−
−
−
V
V
V
2.0 VIH
4.5 or
6.0 VIL
IO = −20 µA
VOH
VOL
VOL
HIGH level
output voltage
driver outputs
3.98 4.32
5.48 5.81
−
−
3.84
5.34
−
−
3.70
5.20
−
−
V
V
4.5 VIH
6.0 or
VIL
IO = −8 mA
IO = −10 mA
LOW level
output voltage
all outputs
−
−
−
0
0
0
0.1
0.1
0.1
−
−
−
0.1
0.1
0.1
−
−
−
0.1
0.1
0.1
V
V
V
2.0 VIH
4.5 or
6.0 VIL
IO = 20 µA
LOW level
output voltage
driver outputs
−
−
0.15 0.26
0.15 0.26
−
−
0.33
0.33
−
−
0.40
0.40
V
V
4.5 VIH
6.0 or
VIL
IO = 8 mA
IO = 10 mA
September 1993
6
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
TEST CONDITION
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN TYP MAX MIN MAX MIN MAX
t
PHL/tPLH propagation
−
−
−
69
25
20
210
42
36
−
−
−
265
53
45
−
−
−
315
63
54
ns
ns
ns
2.0
4.5
6.0
Fig.8
delay
MR to DIR,
DOR
tPHL
propagation
delay
MR to Qn
−
−
−
52
19
15
160
32
27
−
−
−
200
40
34
−
−
−
240
48
41
ns
ns
ns
2.0
4.5
6.0
Fig.8
tPHL/tPLH propagation
delay
−
−
−
66
24
19
205
41
35
−
−
−
255
51
43
−
−
−
310
62
53
ns
ns
ns
2.0
4.5
6.0
Fig.6
SI to DIR
tPHL/tPLH propagation
delay
−
−
−
94
34
27
290
58
49
−
−
−
365
73
62
−
−
−
435
87
74
ns
ns
ns
2.0
4.5
6.0
Fig.9
SO to DOR
t
PHL/tPLH propagation
delay
−
−
−
11
4
3
35
7
6.0
−
−
−
45
9
8
−
−
−
55
11
9
ns
ns
ns
2.0
4.5
6.0
Fig.10
Fig.14
Fig.10
DOR to Qn
tPHL/tPLH propagation
delay
−
−
−
105
38
30
325
65
55
−
−
−
406
81
69
−
−
−
488
98
83
ns
ns
ns
2.0
4.5
6.0
SO to Qn
tPLH
propagation
delay/ripple
through delay
SI to DOR
−
−
−
2.2
0.8
0.6
7
1.4
1.2
−
−
−
8.8
1.8
1.5
−
−
−
10.5 µs
2.1
1.8
2.0
4.5
6.0
µs
µs
tPLH
propagation
delay/bubble-up −
delay
−
2.8
1.0
0.8
9
1.8
1.5
−
−
−
11.2
2.2
1.9
−
−
−
13.5 µs
2.0
4.5
6.0
Fig.7
2.7
2.3
µs
µs
−
SO to DIR
t
t
t
PZH/tPZL
PHZ/tPLZ
THL/tTLH
3-state output
enable
OE to Qn
−
−
−
44
16
13
150
30
26
−
−
−
190
38
32
−
−
−
225
45
38
ns
ns
ns
2.0
4.5
6.0
Fig.16
Fig.16
Fig.16
Fig.6
3-state output
disable
OE to Qn
−
−
−
50
18
14
150
30
26
−
−
−
190
38
33
−
−
−
225
45
38
ns
ns
ns
2.0
4.5
6.0
output
transition time
−
−
−
14
5
4
60
12
10
−
−
−
75
15
13
−
−
−
90
18
15
ns
ns
ns
2.0
4.5
6.0
tW
SI pulse
width
HIGH or LOW
35
7
6.0
11
4
3
−
−
−
45
9
8
−
−
−
55
11
9
−
−
−
ns
ns
ns
2.0
4.5
6.0
tW
SO pulse
width
HIGH or LOW
70
14
12
22
8
6.0
−
−
−
90
18
15
−
−
−
105
21
18
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.9
September 1993
7
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
T
amb (°C)
TEST CONDITION
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN TYP MAX MIN MAX MIN MAX
tW
DIR pulse width 10
41
15
12
130
26
22
8
4
3
165
33
28
8
4
3
195
39
33
ns
ns
ns
2.0
4.5
6.0
Fig.7
HIGH
5
4
tW
DOR pulse
width HIGH
14
7
6.0
52
19
15
160
32
27
12
6
5
200
40
34
12
6.0
5.0
240
48
41
ns
ns
ns
2.0
4.5
6.0
Fig.10
tW
MR pulse width 120
39
14
11
−
−
−
150
30
26
−
−
−
180
36
31
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.8
LOW
24
20
trem
tsu
th
removal time
MR to SI
80
16
14
24
8
7
−
−
−
100
20
17
−
−
−
120
24
20
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.15
set-up time
Dn to SI
−8
−4
−3
−36
−13
−10
−
−
−
−6
−3
−3
−
−
−
−6
−3
−3
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.13
hold time
Dn to SI
135
27
23
44
16
13
−
−
−
170
34
29
−
−
−
205
41
35
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.13
fmax
maximum
clock pulse
frequency
SI, SO burst
mode
3.6
18
21
9.9
30
36
−
−
−
2.8
14
16
−
−
−
2.4
12
14
−
−
−
MHz 2.0
MHz 4.5
MHz 6.0
Figs 11 and 12
fmax
maximum clock 3.6
pulse frequency 18
9.9
30
36
−
−
−
2.8
14
16
−
−
−
2.4
12
14
−
−
−
MHz 2.0
MHz 4.5
MHz 6.0
Figs 6 and 9
Figs 6 and 9
SI, SO using
flags
21
fmax
maximum clock
−
7.6
23
27
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
MHz 2.0
MHz 4.5
MHz 6.0
pulse frequency −
SI, SO
−
cascaded
September 1993
8
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that VOH and VOL are not
valid for driver output.
They are replaced by the values given below.
Output capability: driver 8 mA.
I
CC category: LSI.
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HCT
Tamb (°C)
−40 to +85 −40 to +125 UNIT
TEST CONDITION
SYMBOL
PARAMETER
+25
MIN TYP MAX MIN MAX MIN MAX
VCC
(V)
VI
OTHER
VOH
HIGH level
output voltage
all outputs
4.4
4.5
−
4.4
3.84
−
−
4.4
3.7
−
−
V
V
V
V
4.5 VIH
IO = −20 µA
or
VIL
VOH
VOL
VOL
HIGH level
output voltage
driver outputs
3.98 4.32
−
−
−
4.5 VIH
IO = −8 mA
IO = 20 µA
IO = 8 mA
or
VIL
LOW level
output voltage
all outputs
−
−
0
0.1
0.1
0.33
0.1
0.4
4.5 VIH
or
VIL
LOW level
0.15 0.26
−
−
4.5 VIH
output voltage
driver outputs
or
VIL
Notes to the HCT DC Characteristics
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
2. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
UNIT LOAD COEFFICIENT
INPUT
UNIT LOAD COEFFICIENT
OE
SI
1
1.5
0.75
1.5
1.5
Dn
MR
SO
September 1993
9
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITION
SYMBOL PARAMETER
−25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN TYP MAX MIN MAX MIN MAX
t
PHL/tPLH propagation
−
30
51
−
53
−
63
ns
4.5
Fig.8
delay
MR to DIR,
DOR
tPHL
propagation
delay
MR to Qn
−
−
−
−
−
−
22
25
36
42
7
38
43
61
72
12
1.4
−
−
−
−
−
−
48
−
−
−
−
−
−
57
ns
ns
ns
ns
ns
µs
4.5
4.5
4.5
4.5
4.5
4.5
Fig.8
tPHL/tPLH propagation
delay
54
65
Fig.6
SI to DIR
tPHL/tPLH propagation
delay
76
92
Fig.9
SO to DOR
t
PHL/tPLH propagation
delay
90
108
18
Fig.14
Fig.10
Fig.10
SO to Qn
tPHL/tPLH propagation
delay
15
DOR to Qn
tPLH
propagation
delay/ripple
through delay
SI to DOR
0.8
1.75
2.1
tPLH
propagation
delay/bubble-up
delay
−
1
1.8
−
2.25
−
2.7
µs
4.5
Fig.7
SO to DIR
t
t
t
PZH/tPZL
PHZ/tPLZ
THL/tTLH
3-state output
enable time
OE to Qn
−
−
16
19
30
30
−
−
38
38
−
−
45
45
ns
ns
4.5
4.5
Fig.16
Fig.16
3-state output
disable time
OE to Qn
outputtransition
time
−
5
12
−
−
15
−
−
18
−
ns
ns
ns
ns
4.5
4.5
4.5
4.5
Fig.16
Fig.6
Fig.9
Fig.7
tW
tW
tW
SI pulse width
HIGH or LOW
9
5
6
8
SO pulse width 14
HIGH or LOW
8
−
18
4
−
21
4
−
DIR pulse width 5
HIGH
17
29
36
44
September 1993
10
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Tamb (°C)
TEST CONDITION
SYMBOL PARAMETER
−25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN TYP MAX MIN MAX MIN MAX
tW
DOR pulse
width
7
21
36
6.0
45
6.0
54
ns
4.5
Fig.10
HIGH
tW
MR pulse width 26
LOW
15
10
−16
18
30
−
−
−
−
−
33
23
−4
38
14
−
−
−
−
−
39
27
−4
45
12
−
−
−
−
−
ns
ns
ns
ns
4.5
4.5
4.5
4.5
Fig.8
trem
tsu
removal time
MR to SI
18
−5
30
18
Fig.15
set-up time
Dn to SI
Fig.13
th
hold time
Dn to SI
Fig.13
fmax
maximum
clock pulse
frequency
SI, SO burst
mode
MHz 4.5
MHz 4.5
MHz 4.5
Figs 11 and 12
fmax
maximum
clock pulse
frequency
SI, SO using
flags
18
30
23
−
−
14
−
−
12
−
−
Figs 6 and 9
Figs 6 and 9
fmax
maximum
clock pulse
frequency
SI, SO
−
−
−
cascaded
September 1993
11
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
1st word
2nd word
64th word
1/f max
(1)
(1)
V
M
V
2
SI INPUT
M
4
6
t
W
t
PHL
t
PLH
1
5
DIR OUTPUT
3
7
D
INPUT
n
MGA659
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum
pulse frequency.
Notes to Fig.6
1. DIR initially HIGH; FIFO is prepared for valid data
2. SI set HIGH; data loaded into input stage
3. DIR goes LOW, input stage “busy”
4. SI set LOW; data from first location “ripple through”
5. DIR goes HIGH, status flag indicates FIFO prepared for additional data
6. Repeat process to load 2nd word through to 64th word into FIFO
DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
September 1993
12
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
With FIFO full; SI held HIGH in anticipation of empty location
(1)
2
SO INPUT
SI INPUT
V
M
(1)
1
V
M
5
t
t
PLH
W
bubble - up
delay
(1)
DIR OUTPUT
V
M
3
4
MGA660
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
Notes to Fig.7
1. FIFO is initially full, shift-in is held HIGH
2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins
3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input
4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
September 1993
13
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Master reset applied with FIFO full
handbook, halfpage
(1)
MR INPUT
2
V
M
t
W
t
t
PLH
PHL
(1)
V
3
DIR OUTPUT
DOR OUTPUT
M
M
1
4
(1)
V
t
PHL
Q
OUTPUT
5
n
MGA668
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the MR input to DIR, DOR and Qn output propagation delays and the MR pulse width.
Notes to Fig.8
1. DIR LOW, output ready HIGH; assume FIFO is full
2. MR pulse LOW; clears FIFO
3. DIR goes HIGH; flag indicates input prepared for valid data
4. DOR goes LOW; flag indicates FIFO empty
5. Qn outputs go LOW (only last bit will be reset).
September 1993
14
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
1st SO pulse
1/f
2nd SO pulse
64th SO pulse
max
V
(1)
(1)
V
2
SO INPUT
M
M
4
6
t
W
t
PHL
t
PLH
1
5
(1)
DOR OUTPUT
V
M
3
7
Q
OUTPUT
1st word
2nd word
64th word
n
MGA661
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the SO input to DOR output propagation delay. The SO pulse widths and maximum
pulse frequency.
Notes to Fig.9
1. DOR HIGH; no data transfer in progress, valid data is present at output stage
2. SO set HIGH; results in DOR going LOW
3. DOR goes LOW; output stage “busy”
4. SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input
stage
5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay
6. Repeat process to unload the 3rd through to the 64th word from FIFO
7. DOR remains LOW; FIFO is empty.
September 1993
15
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
With FIFO empty; SO is held HIGH in anticipation
(1)
2
SI INPUT
V
M
(1)
1
6
SO INPUT
DOR OUTPUT
V
M
t
t
PLH
W
ripple through
delay
(1)
4
3
5
V
M
t
t
PHL PLH
Q
OUTPUT
n
MGA658
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation
delay from the DOR pulse to the Qn output.
Notes to Fig.10
1. FIFO is initially empty, SO is held HIGH
2. SI pulse; loads data into FIFO and initiates ripple through process
3. DOR flag signals the arrival of valid data at the output stage
4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the
DOR pulse to the Qn output
5. DOR goes LOW; data shift-out is complete, FIFO is empty again
6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.
September 1993
16
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Shift-in operation; high-speed burst mode
1/f
max
t
W
(1)
V
SI INPUT
M
D
INPUT
n
DIR OUTPUT
MGA662
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing SI minimum pulse width and maximum pulse frequency, in high-speed shift-in burst
mode.
Note to Fig.11
In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications.
The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which
would overflow the storage capacity of the FIFO is ignored.
September 1993
17
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Shift-out operation; high-speed burst mode
1/f
max
t
W
(1)
V
SO INPUT
M
Q
OUTPUT
n
DOR OUTPUT
MGA663
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out
burst mode.
Note to Fig.12
In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW
specifications. The DOR flag is a don't care condition and an SO pulse can be applied without regard to the flag.
September 1993
18
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
(1)
D
INPUT
V
t
n
M
t
su
su
t
t
h
h
(1)
V
SI INPUT
M
MGA657
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.13 Waveforms showing hold and set-up times for Dn input to SI input.
(1)
V
SO INPUT
M
t
t
PHL
PLH
(1)
V
Q
OUTPUT
M
n
t
t
MGA664
TLH
THL
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing SO input to Qn output propagation delays and output transition time.
September 1993
19
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
handbook, halfpage
MR INPUT
(1)
V
M
t
rem
(1)
SI INPUT
V
M
MGA665
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.15 Waveform showing the MR input to SI input removal time.
t
t
r
f
90 %
(1)
OE INPUT
V
M
10 %
t
t
PLZ
PZL
Q
OUTPUT
n
(1)
M
LOW - to - OFF
OFF - to - LOW
V
M
10 %
t
t
PZH
PHZ
90 %
Q
OUTPUT
n
(1)
HIGH - to - OFF
OFF - to - HIGH
V
outputs
enabled
outputs
disabled
outputs
enabled
MGA656
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.16 Waveforms showing the 3-state enable and disable times for input OE.
September 1993
20
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
APPLICATION INFORMATION
OE
DOR
SI
SI OE DOR
SI OE DOR
Q
Q
D
D
D
D
D
D
D
D
0
1
2
3
0
1
2
3
0
1
2
3
0
Q
Q
Q
Q
Q
Q
1
2
3
7403
7403
DIR MR SO
DIR MR SO
8-bit
data
8-bit
data
SI OE DOR
Q
SI OE DOR
Q
D
D
D
D
D
D
D
D
0
1
2
3
0
1
2
3
0
0
1
2
3
Q
Q
Q
Q
Q
Q
1
2
3
7403
7403
DIR MR SO
DIR MR SO
DIR
MR
SO
MGA684
Fig.17 Expanded FIFO (parallel and serial) for increased word length; 8 bits wide x 64 n-bits.
September 1993
21
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
4
D
Q
4
DATA INPUT
DATA OUTPUT
n
n
COMPOSITE
DIR
COMPOSITE
DOR
DIR
DOR
7403
FLAG
FLAG
SO
OE
SO
OE
SI
MR
SI
MR
DIR
SI
DOR
SO
7403
MR
OE
DATA INPUT
4
4
DATA OUTPUT
Q
n
D
n
MGA678
Fig.18 Expanded FIFO for increased word length; 64 words x 10 bits.
Note to Fig.18
The “7403” is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of
an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay
on the flags.
September 1993
22
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
4
Q
4
D
n
n
DIR
DOR
7403
Q
D
D
Q
SO
OE
SI
74
74
composite
DIR
composite
DOR
CP
CP
MR
Q
Q
Q
Q
D
D
DIR
SI
DOR
SO
CP
CP
SI
SO
OE
Q
Q
R
R
7403
MR
MR
OE
MGA683
4
4
D
Q
n
n
Fig.19 Expanded FIFO for increased word length.
Note to Fig.19
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in
cycles are started or if SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are
started (see Figs 7 and 10).
September 1993
23
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
and DnB are satisfied by the DORA
pulse width and the timing between
the rising edge of DORA and QnA
After a second ripple through delay,
data arrives at the output of FIFOB.
for FIFOA. One word is transferred
from the output of FIFOA to the input
of FIFOB. The requirements of the
SOA pulse for FIFOA is satisfied by
the pulse width of DORB. After a
second bubble-up delay an empty
space arrives at DnA, at which time
DIRA goes HIGH. Figure 23 shows
the waveforms at all external nodes of
both FIFOs during a complete shift-in
and shift-out sequence.
Expanded format
Figure 20 shows two cascaded FIFOs
providing a capacity of 128 words x
4 bits. Figure 21 shows the signals on
the nodes of both FIFOs after the
application of a SI pulse, when both
FIFOs are initially empty. After a
ripple through delay, data arrives at
the output of FIFOA. Due to SOA
being HIGH, a DORA pulse is
.
Figure 22 shows the signals on the
nodes of both FIFOs after the
application of a SOB pulse, when both
FIFOs are initially full. After a
bubble-up delay a DIRB pulse is
generated, which acts as a SOA pulse
generated. The requirements of SIB
DOR
SO
SI
DOR
SO
Q
DOR
SO
B
B
B
A
A
DIR
B
SI
SI
7403
FIFO A
7403
nB
4
A
DATA OUTPUT
FIFO B
DIR
DIR
Q
4
D
nB
A
nA
DATA INPUT
4
D
nA
MR
OE
MR
OE
MR
OE
MGA679
Fig.20 Cascading for increased word capacity; 128 words x 4 bits.
Note to Fig.20
The “7403” is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figures 21 and 22 demonstrate the intercommunication timing between
FIFOA and FIFOB. Figure 23 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and
shifted empty again.
September 1993
24
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
(1)
DIR
SI
V
A
M
(1)
2
V
A
M
ripple through
delay
4
(1)
SI
DOR
V
5
B
A
M
(1)
SO
1
A
DIR
Q
V
6
B
M
D
3
nA nB
ripple through
delay
(1)
DOR
7
V
B
M
Q
nB
MGA666
Fig.21 FIFO to FIFO communication; input timing under empty condition.
Notes to Fig.21
1. FIFOA and FIFOB initially empty, SOA held HIGH in anticipation of data
2. Load one word into FIFOA; SI pulse applied, results in DIR pulse
3. Data-out A/data-in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag,
meeting data input set-up requirements of FIFOB
4. DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data
output ready pulse, data is shifted into FIFOB
5. DIRB and SOA go LOW; flag indicates input stage of FIFOB is busy, shift-out of FIFOA is complete
6. DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in
anticipation of additional data
7. DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB
output stage.
September 1993
25
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
(1)
DOR
V
M
B
(1)
2
SO
B
V
M
bubble - up
delay
3
(1)
SO
SI
DIR
V
4
B
A
M
(1)
1
5
DOR
Q
V
M
B
A
D
nA nB
bubble - up
delay
6
(1)
DIR
V
A
M
MGA667
Fig.22 FIFO to FIFO communication; output timing under full condition.
Notes to Fig.22
1. FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up
2. Unload one word from FIFOB; SO pulse applied, results in DOR pulse
3. DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse,
data is shifted out of FIFOA
4. DORA and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOB is complete
5. DORA and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting
bubble-up of empty location
6. DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA.
September 1993
26
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
sequence 1
sequence 2
sequence 3
sequence 4
(8)
sequence 5
sequence 6
SO INPUT
B
(3) (4)
(14)
DOR OUTPUT
B
Q
OUTPUT
nB
(5)
(13)
(12)
DIR OUTPUT
B
(9)
(2)
(6)
DOR OUTPUT
A
Q
OUTPUT
nA
(10)
(7)
DIR OUTPUT
A
(1)
(11)
SI INPUT
A
D
INPUT
nA
MR INPUT
MGA687
Fig.23 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.18).
Note to Fig.23
Sequence 1 (both FIFOS empty, starting SHIFT-IN process)
After a MR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no
valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB
is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage
of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3).
When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes
HIGH (4).
September 1993
27
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Sequence 2 (FIFOB runs full)
After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIRB remains LOW due to FIFOB
being full (5). DORA goes LOW due to FIFOA being empty.
Sequence 3 (FIFOA runs full)
When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the output of FIFOA. QnA remains
HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full
(7). Additional pulses have no effect.
Sequence 4 (both FIFOs full, starting SHIFT-OUT process)
SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow two empty
locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the
input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the
second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11).
Sequence 5 (FIFOA runs empty)
At the start of sequence 5 FIFOA contains 63 valid words due to two words being shifted out and one word being shifted
in, in sequence 4. An additional series of SOB pulses are applied. After 63 SOB pulses, all words from FIFOA are shifted
into FIFOB. DORA remains LOW (12).
Sequence 6 (FIFOB runs empty)
After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being empty. After another 63 SOB pulses,
DORB remains LOW due to both FIFOs being empty (14). Additional SOB pulses have no effect. The last word remains
available at the output Qn.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
28
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