74HCT7403D-Q100,51 [NXP]
74HC(T)7403-Q100 - 4-bit x 64-word FIFO register; 3-state SOP 16-Pin;
| 型号： | 74HCT7403D-Q100,51 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)7403-Q100 - 4-bit x 64-word FIFO register; 3-state SOP 16-Pin 先进先出芯片 |
| 文件： | 总32页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC7403-Q100;
74HCT7403-Q100
4-bit x 64-word FIFO register; 3-state
Rev. 1 — 21 September 2012
Product data sheet
1. General description
The 74HC7403-Q100; 74HCT7403-Q100 is an expandable, First-In First-Out (FIFO)
memory organized as 64 words by 4 bits. A guaranteed 15 MHz data-rate makes it ideal
for high-speed applications. A higher data-rate can be obtained in applications where the
status flags are not used (burst-mode). With separate controls for shift-in (SI) and shift-out
(SO), reading and writing operations are completely independent, allowing synchronous
and asynchronous data transfers. Additional controls include a master-reset input (MR),
an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR)
flags indicate the status of the device. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Synchronous or asynchronous operation
30 MHz (typical) shift-in and shift-out rates
Readily expandable in word and bit dimensions
Pinning arranged for easy board layout: input pins directly opposite output pins
Input levels:
For 74HC7403-Q100: CMOS level
For 74HCT7403-Q100: TTL level
3-state outputs
Complies with JEDEC standard JESD7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Applications
High-speed disc or tape controller
Communications buffer
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC7403D-Q100
74HCT7403D-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
5. Functional diagram
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Fig 3. Functional diagram
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
2 of 32
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LOW on S input of the flip-flops FS, FB and FP set Q output to HIGH independent of state on R input
LOW on R input of FF1 to FF64 sets Q output to LOW independent of state on S input
Fig 4. Logic diagram
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
6. Pinning information
6.1 Pinning
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Fig 5. Pin configuration
6.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
output enable input (active LOW)
data-in-ready output
DIR
2
SI
3
shift-in input (active HIGH)
parallel data input
D0 to D3
GND
MR
4, 5, 6, 7
8
ground (0 V)
9
asynchronous master-reset input (active LOW)
data output
Q0 to Q3
DOR
SO
13, 12, 11, 10
14
15
16
data-out-ready output
shift-out input (active LOW)
supply voltage
VCC
7. Functional description
A DIR flag indicates the input stage status, either empty and ready to receive data (DIR =
HIGH) or full and busy (DIR = LOW). When DIR and SI are HIGH, data present at D0 to
D3 is shifted into the input stage; once complete DIR goes LOW. When SI is set LOW,
data is automatically shifted to the output stage or to the last empty location. DIR set
HIGH indicates a FIFO which can receive data.
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
4 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
A DOR flag indicates the output stage status, either data available (DOR = HIGH) or busy
(DOR = LOW). When SO and DOR are HIGH, data is available at the outputs (Q0 to Q3).
When SO is set LOW new data may be shifted into the output stage, once complete DOR
is set HIGH.
7.1 Expanded format
The DOR and DIR signals are used to allow the 74HC7403-Q100; 74HCT7403-Q100 to
be cascaded. Both parallel and serial expansion is possible. (see Figure 18).
Serial expansion is only possible with typical devices.
7.1.1 Parallel expension
Parallel expension is accomplished by logically ANDing the DOR and DIR signals to form
a composite signal.
7.1.2 Serial expension
Parallel expension is accomplished by:
• Tying the data outputs of the first device to the data inputs of the second device.
• Connecting the DOR pin of the first device to the SI pin of the second device.
• Connecting the SO pin of the first device to the DIR pin of the second device.
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
35
+70
70
+150
500
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
65
[1]
-
mW
[1] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
5 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
9. Recommended operating conditions
Table 4.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC7403-Q100
74HCT7403-Q100
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
+25
40
+25
C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
10. Static characteristics
Table 5.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
74HC7403-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 8 mA; VCC = 4.5 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
3.98 4.32
3.84
5.34
IO = 10 mA; VCC = 6.0 V 5.48 5.81
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 8 mA; VCC = 4.5 V
IO = 10 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
V
0.1
V
0.15 0.26
0.15 0.26
0.33
0.33
1.0
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
IOZ
OFF-state
VI = VIH or VIL;
-
-
0.5
-
5.0
-
10.0 A
output current VO = VCC or GND;
VCC = 6.0 V
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
6 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
Table 5.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
Max
Min
Max
Min
Max
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
50
-
500
-
1000 A
CI
input
-
3.5
-
pF
capacitance
74HCT7403-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 8 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 8 mA
0.15 0.26
0.33
1.0
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
1.0
A
IOZ
OFF-state
VI = VIH or VIL; VCC = 5.5 V;
-
-
0.5
-
5.0
-
10
A
output current VO = VCC or GND per input
pin; other inputs at VCC or
GND; IO = 0 A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
50
-
500
-
1000 A
ICC
additional
VI = VCC 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; Dn inputs
per input pin; OE input
per input pin; SI input
per input pin; MR input
per input pin; SO input
-
-
-
-
-
-
75
270
360
540
540
540
-
-
-
-
-
-
338
450
675
675
675
-
-
-
-
-
368
490
735
735
735
A
A
A
A
A
pF
100
150
150
150
3.5
CI
input
capacitance
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
7 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
11. Dynamic characteristics
Table 6.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions
74HC7403-Q100
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ Max Min
Max
Min
Max
[1]
tpd
propagation MR to DIR or DOR; see
delay
Figure 8
VCC = 2.0 V
-
-
-
69
25
20
210
42
-
-
-
265
53
-
-
-
315
63
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
36
45
54
[1]
SI to DIR; see Figure 6
VCC = 2.0 V
-
-
-
-
66
24
15
19
205
41
-
-
-
-
-
255
51
-
-
-
-
-
310
62
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
35
43
53
[1]
SO to DOR; see Figure 9
VCC = 2.0 V
-
-
-
-
94
34
15
27
290
58
-
-
-
-
-
365
73
-
-
-
-
-
435
87
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
49
62
74
[1]
[1]
DOR to Qn; see Figure 10
VCC = 2.0 V
-
-
-
11
4
35
7
-
-
-
45
9
-
-
-
55
11
9
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
6
8
SO to Qn; see Figure 14
VCC = 2.0 V
-
-
-
105 325
-
-
-
406
81
-
-
-
488
98
ns
ns
ns
VCC = 4.5 V
38
30
65
55
VCC = 6.0 V
69
83
tPHL
HIGH to
LOW
propagation
delay
MR to Qn; see Figure 8
VCC = 2.0 V
-
-
-
52
19
15
160
32
-
-
-
200
40
-
-
-
240
48
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
27
34
41
[5]
[6]
tPLH
LOW to
HIGH
propagation
delay
SI to DOR; see Figure 10
VCC = 2.0 V
-
-
-
2.2
0.8
0.6
7
-
-
-
8.8
1.8
1.5
-
-
-
10.5
2.1
ns
ns
ns
VCC = 4.5 V
1.4
1.2
VCC = 6.0 V
1.8
SO to DIR; see Figure 7
VCC = 2.0 V
-
-
-
2.8
1.0
0.8
9
-
-
-
11.2
2.2
-
-
-
13.5
2.7
ns
ns
ns
VCC = 4.5 V
1.8
1.5
VCC = 6.0 V
1.9
2.3
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
8 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
Table 6.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Typ Max Min
Min
Max
Min
Max
[2]
[3]
[4]
ten
tdis
tt
enable time OE to Qn; see Figure 16
VCC = 2.0 V
VCC = 4.5 V
-
-
-
44
16
13
150
30
-
-
-
190
38
-
-
-
225
45
ns
ns
ns
VCC = 6.0 V
26
32
38
disable time OE to Qn; see Figure 16
VCC = 2.0 V
-
-
-
50
18
14
150
30
-
-
-
190
38
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
26
33
38
transition
time
Qn; see Figure 14
VCC = 2.0 V
-
-
-
14
5
60
12
10
-
-
-
75
15
13
-
-
-
90
18
15
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
tW
pulse width SI HIGH or LOW;
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
35
7
11
4
-
-
-
45
9
-
-
-
55
11
9
-
-
-
ns
ns
ns
6
3
8
SO HIGH or LOW;
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
70
14
12
22
8
-
-
-
90
18
15
-
-
-
105
21
-
-
-
ns
ns
ns
VCC = 6.0 V
6
18
DIR HIGH; see Figure 7
VCC = 2.0 V
10
5
41
15
12
130
26
8
4
3
165
33
8
4
3
195
39
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
22
28
23
DOR HIGH; see Figure 10
VCC = 2.0 V
14
7
52
19
15
160
32
12
6
200
40
12
6
240
48
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
27
5
34
5
41
MR LOW; see Figure 8
VCC = 2.0 V
120
24
39
14
11
-
-
-
150
30
-
-
-
180
36
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
20
26
31
trec
recovery
time
MR to SI; see Figure 15
VCC = 2.0 V
80
16
14
24
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
7
17
20
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
9 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
Table 6.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Typ Max Min
Min
Max
Min
Max
tsu
set-up time Dn to SI; see Figure 13
VCC = 2.0 V
VCC = 4.5 V
8
4
3
36
13
10
-
-
-
6
3
3
-
-
-
6
3
3
-
-
-
ns
ns
ns
VCC = 6.0 V
th
hold time
Dn to SI; see Figure 13
VCC = 2.0 V
135
27
5
44
16
13
-
-
-
170
34
-
-
-
205
12
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
29
14
fmax
maximum
frequency
SI, SO burst mode; see
Figure 11 and Figure 12
VCC = 2.0 V
3.6
18
-
9.9
30
30
36
-
-
-
-
2.8
14
-
-
-
-
-
2.4
12
-
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
21
16
14
SI, SO using flags; see
Figure 6 and Figure 9
VCC = 2.0 V
3.6
18
-
9.9
30
30
36
-
-
-
-
2.8
14
-
-
-
-
-
2.4
12
-
-
-
-
-
MHz
MHz
MHz
MHz
V
CC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
21
16
14
SI, SO cascaded; see
Figure 6 and Figure 9
VCC = 2.0 V
VCC = 4.5 V
-
-
-
-
7.6
23
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
pF
VCC = 6.0 V
27
[7]
CPD
power
VI = GND to VCC
475
dissipation
capacitance
74HC_HCT7403_Q100
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Product data sheet
Rev. 1 — 21 September 2012
10 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
Table 6.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions
74HCT7403-Q100
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ Max Min
Max
Min
Max
[1]
[1]
tpd
propagation MR to DIR or DOR; see
delay
Figure 8
VCC = 4.5 V
-
30
51
-
53
-
63
ns
SI to DIR; see Figure 6
VCC = 4.5 V
-
-
25
17
43
-
-
-
54
-
-
-
65
-
ns
ns
VCC = 5 V; CL = 15 pF
SO to DOR; see Figure 9
VCC = 4.5 V
[1]
-
-
36
17
61
-
-
-
76
-
-
-
92
-
ns
ns
VCC = 5 V; CL = 15 pF
DOR to Qn; see Figure 10
VCC = 4.5 V
[1]
[1]
-
-
-
7
12
72
38
-
-
-
15
90
48
-
-
-
18
108
57
ns
ns
ns
SO to Qn; see Figure 14
VCC = 4.5 V
42
22
tPHL
HIGH to
LOW
propagation
delay
MR to Qn; see Figure 8
VCC = 4.5 V
[5]
[6]
[2]
[3]
[4]
tPLH
LOW to
HIGH
propagation
delay
SI to DOR; see Figure 10
VCC = 4.5 V
-
-
-
-
-
0.8
1.0
16
19
5
1.4
1.8
30
-
-
-
-
-
1.75
2.25
38
-
-
-
-
-
2.1
2.7
45
ns
ns
ns
ns
ns
SO to DIR; see Figure 7
VCC = 4.5 V
ten
tdis
tt
enable time OE to Qn; see Figure 16
VCC = 4.5 V
disable time OE to Qn; see Figure 16
VCC = 4.5 V
30
38
45
transition
time
Qn; see Figure 14
VCC = 4.5 V
12
15
18
tW
pulse width SI HIGH or LOW;
see Figure 6
VCC = 4.5 V
9
5
-
6
-
8
-
ns
SO HIGH or LOW;
see Figure 9
VCC = 4.5 V
14
5
8
-
18
4
-
21
4
-
ns
ns
ns
ns
DIR HIGH; see Figure 7
VCC = 4.5 V
17
21
15
29
36
-
36
45
-
44
54
-
DOR HIGH; see Figure 10
VCC = 4.5 V
7
6
6
MR LOW; see Figure 8
VCC = 4.5 V
26
33
39
74HC_HCT7403_Q100
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Product data sheet
Rev. 1 — 21 September 2012
11 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
Table 6.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Typ Max Min
Min
18
Max
Min
27
Max
trec
recovery
time
MR to SI; see Figure 15
VCC = 4.5 V
10
16
18
-
-
-
23
4
38
-
-
-
-
-
-
ns
ns
ns
tsu
set-up time Dn to SI; see Figure 13
VCC = 4.5 V
5
4
th
hold time
Dn to SI; see Figure 13
VCC = 4.5 V
30
45
fmax
maximum
frequency
SI, SO burst mode; see
Figure 11 and Figure 12
VCC = 4.5 V
18
-
30
30
-
-
14
-
-
-
12
-
-
-
MHz
MHz
VCC = 5 V; CL = 15 pF
SI, SO using flags; see
Figure 6 and Figure 9
VCC = 4.5 V
18
-
30
30
-
-
14
-
-
-
12
-
-
-
MHz
MHz
VCC = 5 V; CL = 15 pF
SI, SO cascaded; see
Figure 6 and Figure 9
VCC = 4.5 V
-
-
23
-
-
-
-
-
-
-
-
-
-
MHz
pF
[7]
CPD
power
VI = GND to VCC 1.5 V
490
dissipation
capacitance
[1] tpd is the same as tPLH and tPHL
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
.
.
[5] This is the ripple through delay.
[6] This is the bubble-up delay.
[7]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT7403_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
12 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
12. Waveforms
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2 34"
ꢒꢂꢕ
1
1
ꢐꢋꢅꢅꢋꢛ%&ꢖ
ꢑ
ꢒꢁꢕ
ꢒꢈꢕ
*
*
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%)(
*
%()
ꢒꢇꢕ
ꢒꢀꢕ
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ꢒꢃꢕ
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ꢀꢁꢂꢃꢎꢆ
Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
Shifting in sequence FIFO empty to FIFO full
(1) DIR initially HIGH; FIFO is prepared for valid data
(2) SI set HIGH; data loaded into input stage
(3) DIR goes LOW; input stage “busy”
(4) SI set LOW; data from first location “ripple through”
(5) DIR goes HIGH; status flag indicates FIFO prepared for additional data
(6) Repeat process to load 2nd word through to 64th word into FIFO; DIR remains LOW; with attempt to shift into full FIFO, no data
transfer occurs.
Fig 6. Propagation delay SI input to DIR output, the SI pulse width and the SI maximum frequency
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
13 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
ꢒꢂꢕ
1
ꢑ
ꢐꢎꢅꢅꢋꢛ%&ꢖ
1
ꢒꢀꢕ
ꢐꢋꢅꢅꢋꢛ%&ꢖ
ꢑ
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ꢑ
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ꢀꢁꢂꢃꢃꢌ
ꢒꢃꢕ
Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
With FIFO full; SI held HIGH in anticipation of empty location
(1) FIFO is initially full, shift-in is held HIGH
(2) SO pulse; data in output stage is unloaded, “bubble-up” process of empty location begins
(3) DIR HIGH; when empty location reaches input stage, flag indicates that FIFO is prepared for data input
(4) DIR returns to LOW; data returns to LOW; data shift-in to empty location is complete, FIFO is full again
(5) SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full
Fig 7. Bubble-up delay SO input to DIR output and the DIR pulse width.
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
14 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
1
ꢑ
ꢒꢂꢕ
ꢑꢌꢅꢅꢋꢛ%&ꢖ
*
>
*
%()
1
ꢒꢃꢕ
ꢑ
ꢑ
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ꢊꢎꢌꢅꢅꢎ&ꢖ%&ꢖ
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*
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%)(
%)(
ꢒꢁꢕ
1
ꢒꢇꢕ
ꢀꢁꢂꢃꢃꢊ
Measurement points are given in Table 7.
OL and VOH are typical voltage output levels that occur with the output load.
V
Master reset applied with FIFO full
(1) DIR LOW; output ready HIGH; assume that FIFO is full
(2) MR pulse LOW; clears FIFO
(3) DIR goes HIGH; flag indicates input prepared for valid data
(4) DOR goes LOW; flag indicates FIFO empty
(5) Qn outputs go LOW (only last bit is reset)
Fig 8. Propagation delay MR input to DIR output, DOR output and Qn outputs and the MR pulse width.
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
15 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
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ꢀꢓ2
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34"
ꢒꢂꢕ
1
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*
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*
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ꢒꢇꢕ
1
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ꢍ$ꢅꢎ&ꢖ%&ꢖ
ꢑ
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ꢒꢃꢕ
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ꢀꢁꢂꢃꢃꢉ
Measurement points are given in Table 7.
OL and VOH are typical voltage output levels that occur with the output load.
V
(1) DOR HIGH; no data transfer in progress, valid data is present at the output stage
(2) SO set HIGH; result in DOR going LOW
(3) DOR goes LOW; output stage “busy”
(4) SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input stage
(5) DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay
(6) Repeat process to unload the 3rd through the 64th word from FIFO
(7) DOR remains LOW; FIFO is empty
Fig 9. Propagation delay SO input to DOR output, the SO pulse width and the SO maximum frequency.
74HC_HCT7403_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
16 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
1
ꢒꢂꢕ
ꢐꢋꢅꢅꢋꢛ%&ꢖ
ꢑ
ꢒꢀꢕ
1
ꢒꢈꢕ
ꢐꢎꢅꢅꢋꢛ%&ꢖ
ꢑ
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>
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1
ꢒꢃꢕ
ꢒꢇꢕ
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Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
With FIFO empty; SO is held HIGH in anticipation
(1) FIFO is initially empty. SO is held HIGH.
(2) SI pulse; loads data into FIFO and initiates ripple through process
(3) DOR flag signals the arrival of valid data at the output stage
(4) Output transition; data arrives at output stage after the specified propagation delay between the rising and falling edge of the
DOR pulse to the Qn output
(5) DOR goes LOW; data shift-out is completed, FIFO is empty again
(6) SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty
Fig 10. Ripple through delay SI input to DOR output, propagation delay DOR input to Qn outputs and the DOR
pulse width
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Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
Shift-in operation; high speed burst mode
In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications. The DIR
status flag is a “don’t care” condition, and a shift-in pulse can be applied regardless of the flag. An SI pulse which would
overflow the storage capacity of the FIFO is ignored.
Fig 11. Shift-in (SI) pulse width and maximum frequency (SI)
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
17 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
ꢀꢓ2
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34"
*
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ꢐꢎꢅꢅꢋꢛ%&ꢖ
ꢑ
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ꢊꢎꢌꢅꢅꢎ&ꢖ%&ꢖ
ꢀꢁꢂꢃꢃꢏ
Measurement points are given in Table 7.
V
OL and VOH are typical voltage output levels that occur with the output load.
Shift-out operation; high speed burst mode
In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW specifications. The
DOR flag is a “don’t care” condition, and an SO pulse can be applied without regard to the flag.
Fig 12. Shift-in (SO) pulse width and maximum frequency (SO)
1
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-:
-:
*
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8
8
1
ꢑ
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Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the output is permitted to change for predictable output performance
Fig 13. Set-up and hold times
1
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Measurement points are given in Table 7.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 14. Propagation delay shift-out input (SO) to data outputs (Qn) and output transition time
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
18 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
1
ꢑꢌꢅꢅꢋꢛ%&ꢖ
ꢐꢋꢅꢅꢋꢛ%&ꢖ
ꢑ
*
6<A
1
ꢑ
ꢀꢁꢂꢃꢃꢎ
Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 15. Master-reset (MR) to shift-in (SI) recovery time
V
I
OE input
V
M
GND
t
t
PZL
PLZ
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aah078
Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 16. Enable and disable times
Table 7.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC7403-Q100
74HCT7403-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
19 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 8.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 17. Test circuit for measuring switching times
Table 8.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC7403-Q100
VCC
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT7403-Q100 3 V
open
GND
VCC
74HC_HCT7403_Q100
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Product data sheet
Rev. 1 — 21 September 2012
20 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
13. Application information
ꢎꢏ
ꢐꢋ
ꢊꢎꢌ
ꢐꢋ ꢎꢏ ꢊꢎꢌ
ꢐꢋ ꢎꢏ ꢊꢎꢌ
ꢍꢄ
ꢍꢄ
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ꢊꢄ
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ꢊꢀ
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ꢀꢁꢂꢃ
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ꢊꢋꢌ ꢑꢌ ꢐꢎ
0/9.*
74*4
0/9.*
74*4
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ꢐꢋ ꢎꢏ ꢊꢎꢌ
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ꢊꢄ
ꢊꢄ
ꢊꢀ
ꢊꢂ
ꢊꢃ
ꢊꢀ
ꢊꢂ
ꢊꢃ
ꢍꢀ
ꢍꢂ
ꢍꢃ
ꢍꢀ
ꢍꢂ
ꢍꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢊꢋꢌ ꢑꢌ ꢐꢎ
ꢊꢋꢌ ꢑꢌ ꢐꢎ
ꢊꢋꢌ
ꢑꢌ
ꢐꢎ
ꢀꢁꢂꢃꢊꢅ
Fig 18. Expanded FIFO (parallel and serial) for increased word length; 8 bits wide x 64 n-bits
ꢁ
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ꢊ#ꢖ#ꢅꢅꢎ&ꢖ%&ꢖ
ꢔꢎꢑ%ꢎꢐꢋꢖꢏ
ꢊꢋꢌ
ꢔꢎꢑ%ꢎꢐꢋꢖꢏ
ꢊꢎꢌ
ꢊꢋꢌ
ꢊꢎꢌ
ꢀꢁꢂꢃ
!(#ꢜ
!(#ꢜ
ꢐꢎ
ꢎꢏ
ꢐꢎ
ꢎꢏ
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ꢑꢌ
ꢐꢋ
ꢑꢌ
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ꢀꢁꢂꢃ
ꢑꢌ
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ꢎꢏ
ꢍ$
ꢊ#ꢖ#ꢅꢅꢋꢛ%&ꢖ
ꢁ
ꢁ
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ꢀꢁꢂꢃꢄꢊ
The 74HC7403-Q100; 74HCT7403-Q100 is easily expanded to increase word length. Composite DIR and DIR flags are formed
with the addition of an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added
gate delay on the flags.
Fig 19. Expanded FIFO for increased word length; 64 words x 10 bits
74HC_HCT7403_Q100
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Product data sheet
Rev. 1 — 21 September 2012
21 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
ꢁ
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ꢔ%
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ꢁ
ꢁ
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are
started or if the SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are started (see
Figure 7 and Figure 10).
Fig 20. Expanded FIFO for increased word length
74HC_HCT7403_Q100
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Product data sheet
Rev. 1 — 21 September 2012
22 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
13.1 Expanded format
Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 4 bits.
Figure 22 shows the signals on the nodes of both FIFOs after the application of the SI
pulse, when both FIFOs are initially empty. After a ripple through delay, data arrives at the
output of FIFOA. Due to SOA being HIGH, a DORA pulse is generated. The requirements
od SIB and DnB are satisfied by the DORA pulse width and the timing between the rising
edge of DORA and QnA. After a second ripple through delay data arrives at the output of
FIFOB.
Figure 23 shows the signals on the nodes of both FIFOs after the application of the SOB
pulse, when both FIFOs are initially full. After a bubble-up delay, a DIRB pulse is
generated, which acts as a SOA pulse for FIFOA. One word is transferred from the output
of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied
by the pulse width of DORB. After a second bubble-up delay an empty space arrives at
DnA, at which time DIRA goes HIGH. Figure 24 shows the waveforms at all external
nodes of both FIFOs during a complete shift-in and shift-out sequence.
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ꢎꢏ
ꢀꢁꢂꢃꢄꢆ
The 74HC7403-Q100; 74HCT7403-Q100 is easily cascaded to increase word capacity without external circuitry. In cascaded
format, all necessary communications are handled by the FIFOs. Figure 22 and Figure 23 demonstrate the communication
timing between FIFOA and FIFOB. Figure 24 provides an overview of pulses and timing of two cascaded FIFOs, when shifted
full and shifted empty again.
Fig 21. Cascading for increased word capacity; 128 words x 4 bits
74HC_HCT7403_Q100
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Product data sheet
Rev. 1 — 21 September 2012
23 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
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1
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7<;4=
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(1) FIFOA and FIFOB are initially empty, SOA held HIGH in anticipation of data
(2) Load one word into FIFOA; SI pulse; applied. results in DIR pulse
(3) Data-out A/ data-in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag, meeting data
input set-up requirements of FIFOB.
(4) DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data output
ready pulse, data is shifted into FIFOB
(5) DIRB and SOA go LOW; flag indicates that input stage of FIFOB is busy, shift-out of FIFOA is complete
(6) DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in anticipation
of additional data
(7) DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB output
stage
Fig 22. FIFO to FIFO communication; input timing under empty condition
74HC_HCT7403_Q100
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Product data sheet
Rev. 1 — 21 September 2012
24 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
1
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1
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9:99;<ꢅ/ꢅ:,
7<;4=
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1
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7<;4=
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1
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(1) FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up
(2) Unload one word from FIFOB; SO pulse applied, results in DOR pulse
(3) DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse, data is
shifted out of FIFOA
(4) DORA and SIB go LOW; flag indicates that the output stage of FIFOA is busy, shift-in of FIFOB is complete
(5) DORA and SIB go HIGH; flag indicates that valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting
bubble-up of empty location.
(6) DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA
Fig 23. FIFO to FIFO communication; output timing under full condition
74HC_HCT7403_Q100
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Product data sheet
Rev. 1 — 21 September 2012
25 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
-<B:<$A<ꢅꢀ
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ꢊꢋꢌ#ꢅꢎ&ꢖ%&ꢖ
ꢒꢀꢄꢕ
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ꢑꢌꢅꢅꢋꢛ%&ꢖ
ꢀꢁꢂꢃꢊꢄ
See also Section 13.1.1
Fig 24. Waveforms showing the functionality and intercommunication between two FIFOs (refer to Figure 19)
13.1.1 Sequence 1 (both FIFOs empty, starting SHIFT-IN process)
After an MR pulse has been applied, FIFOA and FIFOB are empty. The DOR flags of
FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR
flags are set HIGH due to the FIFOs being ready to accept data. SOB is held HIGH and
two SIA pulses are applied (1). These pulses allow two data words to ripple through the
output stage of FIFOA and the input stage of FIFIB (2). When data arrives at the output of
FIFOB, a DORB pulse is generated (3). When SOB goes LOW, the first bit is shifted out
and a second bit ripples through to the output after which DORB goes high (4).
13.1.2 Sequence 2 (FIFOB runs full)
After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in,
DIRB remains LOW due to FIFOB being full (5). DORA goes LOW due to FIFOA being
empty.
74HC_HCT7403_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
26 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
13.1.3 Sequence 3 (FIFOA runs full)
When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the
output of FIFOA. QnA remains HIGH, being the polarity of the 65th word (6). After the
128th SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no
effect.
13.1.4 Sequence 4 (both FIFOs full, starting SHIFT-OUT)
SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words
and thus allow two empty locations to bubble-up to the input stage of FIFOB, and proceed
to FIFOA (9). When the first empty location arrives at the input of FIFOA, a DIRA pulse is
generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the
second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH
(11).
13.1.5 Sequence 5 (FIFOA runs empty)
At the start of sequence 5, FIFOA contains 63 valid words due to two words being shifted
out and one word being shifted in, in sequence 4. And additional series of SOB pulses are
applied. After 63 SOB pulses, all words from FIFOA are shifted in FIFOB. DORA remains
LOW (12).
13.1.6 Sequence 6 (FIFOB runs empty)
After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being
empty. After another 63 SOB pulses, DORB remains LOW due to both FIFOS being
empty (14). Additional SOB pulses have no effect. The last word remains available at the
output Qn.
74HC_HCT7403_Q100
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Product data sheet
Rev. 1 — 21 September 2012
27 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
14. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 25. Package outline SOT109-1 (SO16)
74HC_HCT7403_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
28 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
15. Abbreviations
Table 9.
Acronym
CMOS
ESD
Abbreviations
Description
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
First In First Out
FIFO
MIL
Military
16. Revision history
Table 10. Revision history
Document ID
Release date Data sheet status
Change notice
Supersedes
74HC_HCT7403_Q100 v.1 20120921
Product data sheet
-
-
74HC_HCT7403_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
29 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
17.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
30 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT7403_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 21 September 2012
31 of 32
74HC7403-Q100; 74HCT7403-Q100
NXP Semiconductors
4-bit x 64-word FIFO register; 3-state
19. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
7.1.1
7.1.2
Functional description . . . . . . . . . . . . . . . . . . . 4
Expanded format . . . . . . . . . . . . . . . . . . . . . . . 5
Parallel expension . . . . . . . . . . . . . . . . . . . . . . 5
Serial expension. . . . . . . . . . . . . . . . . . . . . . . . 5
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9
10
11
12
13
13.1
13.1.1
Application information. . . . . . . . . . . . . . . . . . 21
Expanded format . . . . . . . . . . . . . . . . . . . . . . 23
Sequence 1 (both FIFOs empty, starting
SHIFT-IN process) . . . . . . . . . . . . . . . . . . . . . 26
Sequence 2 (FIFOB runs full). . . . . . . . . . . . . 26
Sequence 3 (FIFOA runs full). . . . . . . . . . . . . 27
Sequence 4 (both FIFOs full, starting
13.1.2
13.1.3
13.1.4
SHIFT-OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Sequence 5 (FIFOA runs empty) . . . . . . . . . . 27
Sequence 6 (FIFOB runs empty) . . . . . . . . . . 27
13.1.5
13.1.6
14
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 28
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 29
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 30
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 31
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 September 2012
Document identifier: 74HC_HCT7403_Q100
相关型号：
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