74HCT7404DB-T [NXP]
IC 64 X 5 OTHER FIFO, PDSO20, FIFO;
| 型号： | 74HCT7404DB-T |
| 厂家： | 
NXP |
| 描述： | IC 64 X 5 OTHER FIFO, PDSO20, FIFO 先进先出芯片 |
| 文件： | 总28页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7404
5-Bit x 64-word FIFO register;
3-state
September 1993
Product specification
Supersedes data of October 1990
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
FEATURES
GENERAL DESCRIPTION
• Synchronous or asynchronous operation
• 3-state outputs
The 74HC/HCT7404 are high-speed Si-gate CMOS
devices specified in compliance with JEDEC standard
no.7A.
• 30 MHz (typical) shift-in and shift-out rates
• Readily expandable in word and bit dimensions
The “7404” is an expandable, First-In First-Out (FIFO)
memory organized as 64 words by 5 bits. A guaranteed
15 MHz data-rate makes it ideal for high-speed
applications. A higher data-rate can be obtained in
applications where the status flags are not used
(burst-mode).
• Pinning arranged for easy board layout: input pins
directly opposite output pins
• Output capability: driver (8 mA)
• ICC category: LSI.
With separate controls for shift-in (SI) and shift-out (SO),
reading and writing operations are completely
APPLICATIONS
independent, allowing synchronous and asynchronous
data transfers. Additional controls include a master-reset
input (MR), an output enable input (OE) and flags. The
data-in-ready (DIR) and data-out-ready (DOR) flags
indicate the status of the device.
• High-speed disc or tape controller
• Communications buffer.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
TYP.
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
HC
HCT
17
tPHL/tPLH propagation delay SO, SI to DIR and DOR
CL = 15 pF; VCC = 5 V
15
30
fmax
CI
maximum clock frequency
30
MHz
pF
input capacitance
3.5
3.5
490
CPD
power dissipation capacitance per package
note 1
475
pF
Note
1. For HC the condition is VI = GND to VCC
.
For HCT the condition is VI = GND to VCC −1.5 V.
ORDERING INFORMATION
PACKAGE
EXTENDED
TYPE NUMBER
PINS
18
PIN POSITION
MATERIAL
plastic
CODE
SOT102
SOT163A
74HC/HCT7404N
74HC/HCT7404D
DIL
20
SO20
plastic
September 1993
2
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
PINNING (SOT102)
PINNING (SOT163A)
SYMBOL
OE
PIN
DESCRIPTION
SYMBOL
OE
PIN
DESCRIPTION
1
output enable input (active
LOW)
1
output enable input (active
LOW)
DIR
2
3
data-in-ready output
DIR
2
3
4
data-in-ready output
shift-in input (active HIGH)
not connected
SI
shift-in input (active HIGH)
SI
DO to D4
GND
MR
4, 5, 6, 7, 8 parallel data inputs
n.c.
9
ground
D0 to D4
GND
MR
5, 6, 7, 8, 9 parallel data inputs
10
asynchronous master-reset
input (active LOW)
10
11
ground
asynchronous master-reset
input (active LOW)
Q4 to Q0
11, 12, 13, data outputs
14, 15
Q4 to Q0
12, 13, 14, data outputs
15, 16
DOR
SO
16
17
18
data-out-ready output
shift-out input (active LOW)
positive supply voltage
n.c.
17
18
19
20
not connected
VCC
DOR
n.c.
data-out ready output
not connected
VCC
positive supply voltage
handbook, halfpage
1
V
OE
DIR
SI
20
19
handbook, halfpage
CC
1
18
17
V
OE
CC
2
3
4
5
6
7
8
9
SO
DIR
2
3
4
5
6
7
8
9
SO
18 DOR
SI
16 DOR
n.c.
n.c.
17
16
15
14
13
12
11
D
0
Q
Q
Q
Q
Q
15
14
13
12
11
10
0
1
2
3
4
D
0
Q
Q
Q
Q
Q
0
1
2
3
4
D
1
7404
7404
D
1
D
2
D
2
D
3
D
3
D
4
D
4
GND
MR
GND 10
MR
MGA670
MGA671
Fig.1 Pin configuration (SOT102).
Fig.2 Pin configuration (SOT163).
September 1993
3
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
1 (1)
handbook, halfpage
(1) 1
handbook, halfpage
FIFO 64 x 5
EN4
1Z3
[IR] 3
2 (2)
OE
[OR] 6
16 (18)
(5) 4
(6) 5
(7) 6
(8) 7
(9) 8
15 (16)
14 (15)
13 (14)
12 (13)
11 (12)
D
D
Q
Q
0
1
0
1
CTR
<
(3) 3
(11) 10
(19) 17
1 ( /C2) CT 64 G1
CT = 0
D
D
D
Q
Q
Q
2
3
4
2
3
4
>
G5
4
CT
0
5
5Z6
(5) 4
(6) 5
(7) 6
(8) 7
(9) 8
2D
15 (16)
14 (15)
13 (14)
12 (13)
11 (12)
(3) 3
DOR
DIR
16 (18)
2 (2)
SI
(19) 17
SO
MR
MGA673
10 (11)
MGA675
Pin numbers between parentheses refer to the SO package.
Pin numbers between parentheses refer to the SO package.
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
Q
(5) 4
(6) 5
(7) 6
(8) 7
(9) 8
D
D
D
D
D
15 (16)
14 (15)
13 (14)
12 (13)
11 (12)
0
1
2
3
4
0
1
2
3
4
Q
Q
Q
Q
INPUT
STAGE
1 x 5 BITS
MAIN FIFO
REGISTER
62 x 5 BITS
OUTPUT
STAGE
1 x 5 BITS
OE
MR
(11) 10
CONTROL LOGIC
DIR
SI
3 (3)
DOR SO
OE
1 (1)
MGA680
2 (2)
16 (18) 17 (19)
Pin numbers between parentheses refer to the SO package.
Fig.5 Functional diagram.
September 1993
4
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
SM1B7
f
September 1993
5
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
outputs (Q0 to Q4). When SO is LOW
FUNCTIONAL DESCRIPTION
Serial Expansion
new data may be shifted into the
output stage, once complete DOR is
set LOW.
The DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D0 to D4 is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
Serial expansion is accomplished by:
• tying the data outputs of the first
device to the data inputs of the
second device
Expanded Format (see Fig.18)
• connecting the DOR pin of the first
device to the SI pin of the second
device
The DOR and DIR signals are used to
allow the ‘7404’ to be cascaded. Both
parallel and serial expansion is
possible. Serial expansion is only
possible with typical devices.
• connecting the SO pin of the first
device to the DIR pin of the second
device.
Parallel Expansion
A DOR flag indicates the output stage
status, either data available
(DOR = HIGH) or busy
Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
(DOR = LOW). When SO and DOR
are HIGH, data is available at the
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI
Output capability: driver 8 mA
ICC category: LSI
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HC
Tamb °C
TEST CONDITION
SYMBOL
PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
(V)
VI
OTHER
MIN TYP MAX MIN MAX MIN MAX
VOH
HIGH level
output voltage
3.98 4.32
5.48 5.81
−
−
3.84
5.34
−
−
3.70
5.20
−
−
V
V
4.5 VIH IO = −8 mA
6
or
IO = −10 mA
VIL
VOL
LOW level
output voltage
−
−
0.15 0.26
0.15 0.26
−
−
0.33
0.33
−
−
0.4
0.4
V
V
4.5 VIH IO = 8 mA
6
or
IO = 10 mA
VIL
September 1993
6
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb °C
TEST CONDITION
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN TYP MAX MIN MAX MIN MAX
t
PHL/tPLH propagation
−
−
−
69
25
20
210
42
36
−
−
−
265
53
45
−
−
−
315
63
54
ns
ns
ns
2.0
4.5
6.0
Fig.9
delay
MR to DIR,
DOR
tPHL
propagation
delay
MR to Qn
−
−
−
52
19
15
160
32
27
−
−
−
200
40
34
−
−
−
240
48
41
ns
ns
ns
2.0
4.5
6.0
Fig.9
tPHL/tPLH propagation
delay
−
−
−
66
24
19
205
41
35
−
−
−
255
51
43
−
−
−
310
62
53
ns
ns
ns
2.0
4.5
6.0
Fig.7
SI to DIR
tPHL/tPLH propagation
delay
−
−
−
94
34
27
290
58
49
−
−
−
365
73
62
−
−
−
435
87
74
ns
ns
ns
2.0
4.5
6.0
Fig.10
Fig.11
Fig.15
Fig.16
SO to DOR
t
PHL/tPLH propagation
delay
−
−
−
11
4
3
35
7
6.0
−
−
−
45
9
8
−
−
−
55
11
9
ns
ns
ns
2.0
4.5
6.0
DOR to Qn
tPHL/tPLH propagation
delay
−
−
−
105
38
30
325
65
55
−
−
−
406
81
69
−
−
−
488
98
83
ns
ns
ns
2.0
4.5
6.0
SO to Qn
tPLH
propagation
delay/ripple
through delay
SI to DOR
−
−
−
2.2
0.8
0.6
7.0
1.4
1.2
−
−
−
8.8
1.8
1.5
−
−
−
10.5 µs
2.1
1.8
2.0
4.5
6.0
µs
µs
tPLH
propagation
delay/bubble-up −
delay SO to
DIR
−
2.8
1.0
0.8
9.0
1.8
1.5
−
−
−
11.2
2.2
1.9
−
−
−
13.5 µs
2.0
4.5
6.0
Fig.8
2.7
2.3
µs
µs
−
t
t
t
PZH/tPZL
PHZ/tPLZ
THL/tTLH
3-state output
enable
OE to Qn
−
−
−
44
16
13
150
30
26
−
−
−
190
38
32
−
−
−
225
45
38
ns
ns
ns
2.0
4.5
6.0
Fig.17
Fig.17
Fig.17
Fig.7
3-state output
disable
OE to Qn
−
−
−
50
18
14
150
30
26
−
−
−
190
38
33
−
−
−
225
45
38
ns
ns
ns
2.0
4.5
6.0
outputtransition
time
−
−
−
14
5
4
60
12
10
−
−
−
75
15
13
−
−
−
90
18
15
ns
ns
ns
2.0
4.5
6.0
tW
SI pulse width
HIGH or LOW
35
7
6
11
4
3
−
−
−
45
9
8
−
−
−
55
11
9
−
−
−
ns
ns
ns
2.0
4.5
6.0
tW
SO pulse width 70
22
8
6
−
−
−
90
18
15
−
−
−
105
21
18
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.10
HIGH or LOW
14
12
September 1993
7
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
T
amb °C
TEST CONDITION
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN TYP MAX MIN MAX MIN MAX
tW
DIR pulse width 10
41
15
12
130
26
22
8
4
3
165
33
28
8
4
3
195
39
33
ns
ns
ns
2.0
4.5
6.0
Fig.8
HIGH
5
4
tW
DOR pulse
width HIGH
14
7
6
52
19
15
160
32
27
12
6
5
200
40
34
12
6
5
240
48
41
ns
ns
ns
2.0
4.5
6.0
Fig.11
Fig.9
tW
MR pulse
width LOW
120
24
20
39
14
11
−
−
−
150
30
26
−
−
−
180
36
31
−
−
−
ns
ns
ns
2.0
4.5
6.0
trem
tsu
th
removal time
MR to SI
80
16
14
24
8
7
−
−
−
100
20
17
−
−
−
120
24
20
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.16
Fig.14
Fig.14
set-up time
Dn to SI
−8
−4
−3
−36
−13
−10
−
−
−
−6
−3
−3
−
−
−
−6
−3
−3
−
−
−
ns
ns
ns
2.0
4.5
6.0
hold time
Dn to SI
135
27
23
44
16
13
−
−
−
170
34
29
−
−
−
205
41
35
−
−
−
ns
ns
ns
2.0
4.5
6.0
fmax
maximum clock 3.6
pulse frequency 18
9.9
30
36
−
−
−
2.8
14
16
−
−
−
2.4
12
14
−
−
−
MHz 2.0
MHz 4.5
MHz 6.0
Fig.12 and
Fig.13
SI, SO burst
mode
21
fmax
maximum clock 3.6
pulse frequency 18
9.9
30
36
−
−
−
2.8
14
16
−
−
−
2.4
12
14
−
−
−
MHz 2.0
MHz 4.5
MHz 6.0
Fig.7 and
Fig.10
SI, SO using
flags
21
fmax
maximum clock
pulse frequency −
SI, SO
−
7.6
23
27
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
MHz 2.0
MHz 4.5
MHz 6.0
Fig.7 and
Fig.10
−
cascaded
September 1993
8
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that VOH and VOL are not
valid for driver output. They are replaced by the values given below.
Output capability: driver 8 mA
ICC category: LSI.
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HCT
Tamb °C
TEST CONDITION
SYMBOL
PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
(V)
VI
OTHER
MIN TYP MAX MIN MAX MIN MAX
VOH
HIGH level
output voltage
3.98 4.32
−
3.84
−
3.7
−
V
V
4.5 VIH
IO = −8 mA
or
VIL
VOL
LOW level
−
0.15 0.26
−
0.33
−
0.40
4.5 VIH
IO = 8 mA
output voltage
or
VIL
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
UNIT LOAD COEFFICIENT
INPUT
UNIT LOAD COEFFICIENT
OE
SI
1
1.5
0.75
1.5
1.5
Dn
MR
SO
September 1993
9
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
T
amb °C
TEST CONDITION
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN TYP MAX MIN MAX MIN MAX
t
PHL/tPLH propagation
−
30
51
−
53
−
63
ns
4.5
Fig.9
delay
MR to DIR,
DOR
tPHL
propagation
delay
MR to Qn
−
−
−
−
−
−
22
25
36
42
7
38
43
61
72
12
1.4
−
−
−
−
−
−
48
−
−
−
−
−
−
57
ns
ns
ns
ns
ns
µs
4.5
4.5
4.5
4.5
4.5
4.5
Fig.9
tPHL/tPLH propagation
delay
54
65
Fig.7
SI to DIR
tPHL/tPLH propagation
delay
76
92
Fig.10
Fig.15
Fig.11
Fig.11
SO to DOR
t
PHL/tPLH propagation
delay
90
108
18
SO to Qn
tPHL/tPLH propagation
delay
15
DOR to Qn
tPLH
propagation
delay/ripple
through delay
SI to DOR
0.8
1.75
2.1
tPLH
propagation
delay/bubble-
up delay
−
1
1.8
−
2.25
−
2.7
µs
4.5
Fig.8
SO to DIR
t
t
t
PZH/tPZL
PHZ/tPLZ
THL/tTLH
3-state output
enable
OE to Qn
−
−
16
19
30
30
−
−
38
38
−
−
45
45
ns
ns
4.5
4.5
Fig.17
Fig.17
3-state output
disable
OE to Qn
output
transition time
−
5
12
−
−
15
−
−
18
−
ns
ns
ns
ns
4.5
4.5
4.5
4.5
Fig.17
Fig.7
tW
tW
tW
SI pulse width
HIGH or LOW
9
5
6
8
SO pulse width 14
HIGH or LOW
8
−
18
4
−
21
4
−
Fig.10
Fig.8
DIR pulse width 5
HIGH
17
29
36
44
September 1993
10
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
T
amb °C
TEST CONDITION
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN TYP MAX MIN MAX MIN MAX
tW
DOR pulse
width HIGH
7
21
15
10
−16
18
30
36
6
45
6
54
ns
ns
ns
ns
ns
4.5
Fig.11
tW
MR pulse
width LOW
26
18
−5
30
18
−
33
23
−4
38
14
−
39
27
−4
45
12
−
4.5
4.5
4.5
45
Fig.9
trem
tsu
th
removal time
MR to SI
−
−
−
Fig.16
set-up time
Dn to SI
−
−
−
Fig.14
hold time
Dn to SI
−
−
−
Fig.14
fmax
maximum
clock pulse
frequency
SI, SO burst
mode
−
−
−
MHz 4.5
MHz 4.5
MHz 4.5
Fig.12 and Fig.13
fmax
maximum
clock pulse
frequency
SI, SO using
flags
18
30
23
−
−
14
−
−
12
−
−
Fig.7 and Fig.10
Fig.7 and Fig.10
fmax
maximum
clock pulse
frequency
SI, SO
−
−
−
cascaded
September 1993
11
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
1st word
2nd word
64th word
1/f max
(1)
(1)
V
M
V
2
SI INPUT
M
4
6
t
W
t
PHL
t
PLH
1
5
DIR OUTPUT
3
7
D
INPUT
n
MGA659
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.7 Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum
pulse frequency.
Notes to Fig.7
1. DIR initially HIGH; FIFO is prepared for valid data
2. SI set HIGH; data loaded into input stage
3. DIR goes LOW, input stage “busy”
4. SI set LOW; data from first location “ripple through”
5. DIR goes HIGH, status flag indicates FIFO prepared for additional data
6. Repeat process to load 2nd word through to 64th word into FIFO
DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
September 1993
12
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
With FIFO full; SI held HIGH in anticipation of empty location
(1)
2
SO INPUT
SI INPUT
V
M
(1)
1
V
M
5
t
t
PLH
W
bubble - up
delay
(1)
DIR OUTPUT
V
M
3
4
MGA660
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.8 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
Notes to Fig.8
1. FIFO is initially full, shift-in is held HIGH
2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins
3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input
4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
September 1993
13
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
Master reset applied with FIFO full
handbook, halfpage
(1)
MR INPUT
2
V
M
t
W
t
t
PLH
PHL
(1)
V
3
DIR OUTPUT
DOR OUTPUT
M
M
1
4
(1)
V
t
PHL
Q
OUTPUT
5
n
MGA668
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.9 Waveforms showing the MR input to DIR, DOR and Qn output propagation delays and the MR pulse width.
Notes to Fig.9
1. DIR LOW, output ready HIGH; assume FIFO is full
2. MR pulse LOW; clears FIFO
3. DIR goes HIGH; flag indicates input prepared for valid data
4. DOR goes LOW; flag indicates FIFO empty
5. Qn outputs go LOW (only last bit will be reset).
September 1993
14
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
1st SO pulse
1/f
2nd SO pulse
64th SO pulse
max
V
(1)
(1)
V
2
SO INPUT
M
M
4
6
t
W
t
PHL
t
PLH
1
5
(1)
DOR OUTPUT
V
M
3
7
Q
OUTPUT
1st word
2nd word
64th word
n
MGA661
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.10 Waveforms showing the SO input to DOR output propagation delay, the SO pulse widths and maximum
pulse frequency.
Notes to Fig.10
1. DOR HIGH; no data transfer in progress, valid data is present at output stage
2. SO set HIGH; results in DOR going LOW
3. DOR goes LOW; output stage “busy”
4. SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input
stage
5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay
6. Repeat process to unload the 3rd through to the 64th word from FIFO.
7. DOR remains LOW; FIFO is empty.
September 1993
15
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
With FIFO empty; SO is held HIGH in anticipation
(1)
2
SI INPUT
V
M
(1)
1
6
SO INPUT
DOR OUTPUT
V
M
t
t
PLH
W
ripple through
delay
(1)
4
3
5
V
M
t
t
PHL PLH
Q
OUTPUT
n
MGA669
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.11 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation
delay from the DOR pulse to the Qn output.
Notes to Fig.11
1. FIFO is initially empty, SO is held HIGH
2. SI pulse; loads data into FIFO and initiates ripple through process
3. DOR flag signals the arrival of valid data at the output stage
4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the
DOR pulse to the Qn output
5. DOR goes LOW; data shift-out is complete, FIFO is empty again
6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.
September 1993
16
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
Shift-in operation; high-speed burst mode
1/f
max
t
W
(1)
V
SI INPUT
M
D
INPUT
n
DIR OUTPUT
MGA662
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.12 Waveforms showing SI minimum pulse width and maximum pulse frequency, in high-speed shift-in burst
mode.
Note to Fig.12
In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications.
The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which
would overflow the storage capacity of the FIFO is ignored.
September 1993
17
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
Shift-out operation; high-speed burst mode
1/f
max
t
W
(1)
V
SO INPUT
M
Q
OUTPUT
n
DOR OUTPUT
MGA663
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.13 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out
burst mode.
Note to Fig.13
In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW
specifications. The DOR flag is a don't care condition and an SO pulse can be applied without regard to the flag.
September 1993
18
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
(1)
D
INPUT
V
t
n
M
t
su
su
t
t
h
h
(1)
V
SI INPUT
M
MGA657
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC.
VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.14 Waveforms showing hold and set-up times for Dn input to SI input.
(1)
V
SO INPUT
M
t
t
PHL
PLH
(1)
V
Q
OUTPUT
M
n
t
t
MGA664
TLH
THL
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.15 Waveforms showing SO input to Qn output propagation delays and output transition time.
handbook, halfpage
(1)
V
MR INPUT
M
t
rem
(1)
SI INPUT
V
M
MGA665
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.16 Waveform showing the MR input to SI input removal time.
September 1993
19
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
t
t
r
f
90 %
(1)
OE INPUT
V
M
10 %
t
t
PLZ
PZL
Q
OUTPUT
n
(1)
M
LOW - to - OFF
OFF - to - LOW
V
M
10 %
t
t
PZH
PHZ
90 %
Q
OUTPUT
n
(1)
HIGH - to - OFF
OFF - to - HIGH
V
outputs
enabled
outputs
disabled
outputs
enabled
MGA656
(1) HC
HCT
:
:
VM = 50%; VI = GND to VCC
VM = 1.3 V; VI = GND to 3 V.
.
Fig.17 Waveforms showing the 3-state enable and disable times for input OE.
September 1993
20
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
APPLICATION INFORMATION
OE
DOR
SI
SI OE DOR
SI OE DOR
Q
Q
D
D
D
D
D
D
D
D
D
D
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
Q
Q
Q
Q
Q
Q
Q
Q
1
2
3
4
7404
7404
DIR MR SO
DIR MR SO
10-bit
data
10-bit
data
SI OE DOR
Q
SI OE DOR
Q
D
D
D
D
D
D
D
D
D
D
0
1
2
3
4
0
1
2
3
4
0
1
0
1
Q
Q
Q
Q
2
3
4
7404
2
3
4
7404
Q
Q
Q
Q
DIR MR SO
DIR MR SO
DIR
MR
SO
MGA686
Fig.18 Expanded FIFO (parallel and serial) for increased word length; 10 bits wide × 64 n-bits.
September 1993
21
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
5
D
Q
5
DATA INPUT
DATA OUTPUT
n
n
COMPOSITE
DIR
COMPOSITE
DOR
DIR
DOR
7404
FLAG
FLAG
SO
OE
SO
OE
SI
MR
SI
MR
DIR
SI
DOR
SO
7404
MR
OE
DATA INPUT
5
5
DATA OUTPUT
Q
n
D
n
MGA681
Fig.19 Expanded FIFO for increased word length; 64 words × 10 bits.
Note to Fig.19
The ”7404” is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of
an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay
on the flags.
September 1993
22
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
5
D
Q
5
n
n
DIR
DOR
7404
Q
D
D
Q
SI
SO
OE
74
74
composite
DOR
composite
DIR
CP
CP
MR
Q
Q
Q
Q
D
D
DIR
SI
DOR
SO
CP
CP
SI
SO
OE
Q
Q
R
R
7404
MR
MR
OE
MGA685
5
5
D
Q
n
n
Fig.20 Expanded FIFO for increased word length.
Note to Fig.20
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in
cycles are started or if SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are
started (see Fig.8 and Fig.10).
Expanded format
Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 5 bits. Figure 22 shows the signals on the
nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially empty. After a ripple through delay,
data arrives at the output of FIFOA. Due to SOA being HIGH, a DORA pulse is generated. The requirements of SIB and
DnB are satisfied by the DORA pulse width and the timing between the rising edge of DORA and QnA. After a second ripple
through delay, data arrives at the output of FIFOB.
Figure 23 shows the signals on the nodes of both FIFOs after the application of a SOB pulse, when both FIFOs are initially
full. After a bubble-up delay a DIRB pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred
from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse
width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH.
Figure 24 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
September 1993
23
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
DOR
A
SI
DOR
SO
Q
DOR
SO
B
B
B
DIR
SO
A
B
SI
SI
7404
7404
nB
5
A
DATA OUTPUT
FIFO A
FIFO B
DIR
DIR
Q
5
D
nB
A
nA
DATA INPUT
5
D
nA
MR
OE
MR
OE
MR
OE
MGA682
Fig.21 Cascading for increased word capacity; 128 word × 5 bits.
Note to Fig.21
The “7404” is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figures 22 and 23 demonstrate the intercommunication timing between
FIFOA and FIFOB. Figure 24 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and
shifted empty again.
September 1993
24
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
(1)
DIR
SI
V
A
M
(1)
2
V
A
M
ripple through
delay
4
(1)
SI
DOR
V
5
B
A
M
(1)
SO
1
A
DIR
Q
V
6
B
M
D
3
nA nB
ripple through
delay
(1)
DOR
7
V
B
M
Q
nB
MGA666
Fig.22 FIFO to FIFO communication; input timing under empty condition.
Notes to Fig.22
1. FIFOA and FIFOB initially empty, SOA held HIGH in anticipation of data
2. Load one word into FIFOA; SI pulse applied, results in DIR pulse
3. Data-out A/data-in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag,
meeting data input set-up requirements of FIFOB
4. DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data
output ready pulse, data is shifted into FIFOB
5. DIRB and SOA go LOW; flag indicates input stage of FIFOB is busy, shift-out of FIFOA is complete
6. DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in
anticipation of additional data
7. DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB
output stage.
September 1993
25
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
(1)
DOR
V
M
B
(1)
2
SO
B
V
M
bubble - up
delay
3
(1)
SO
SI
DIR
V
4
B
A
M
(1)
1
5
DOR
Q
V
M
B
A
D
nA nB
bubble - up
delay
6
(1)
DIR
V
A
M
MGA667
Fig.23 FIFO to FIFO communication; output timing under full condition.
Notes to Fig.23
1. FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up
2. Unload one word from FIFOB; SO pulse applied, results in DOR pulse
3. DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse,
data is shifted out of FIFOA
4. DORA and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOB is complete
5. DORA and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting
bubble-up of empty location
6. DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA.
September 1993
26
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
sequence 1
sequence 2
sequence 3
sequence 4
(8)
sequence 5
sequence 6
SO INPUT
B
(3) (4)
(14)
DOR OUTPUT
B
Q
OUTPUT
nB
(5)
(13)
(12)
DIR OUTPUT
B
(9)
(2)
(6)
DOR OUTPUT
A
Q
OUTPUT
nA
(10)
(7)
DIR OUTPUT
A
(1)
(11)
SI INPUT
A
D
INPUT
nA
MR INPUT
MGA687
Fig.24 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.19).
Note to Fig.24
Sequence 1 (both FIFOS empty, starting SHIFT-IN process)
After a MR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no
valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB
is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage
of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3).
When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes
HIGH (4).
September 1993
27
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
Sequence 2 (FIFOB runs full)
Sequence 4 (both FIFOs full,
Sequence 5 (FIFOA runs empty)
starting SHIFT-OUT process)
After the MR pulse, a series of 64 SI
pulses are applied. When 64 words
are shifted in, DIRB remains LOW due
to FIFOB being full (5). DORA goes
LOW due to FIFOA being empty.
At the start of sequence 5 FIFOA
contains 63 valid words due to two
words being shifted out and one word
being shifted in, in sequence 4. An
additional series of SOB pulses are
applied. After 63 SOB pulses, all
words from FIFOA are shifted into
FIFOB. DORA remains LOW (12).
SIA is held HIGH and two SOB pulses
are applied (8). These pulses shift out
two words and thus allow two empty
locations to bubble-up to the input
stage of FIFOB, and proceed to FIFOA
(9). When the first empty location
arrives at the input of FIFOA, a DIRA
pulse is generated (10) and a new
word is shifted into FIFOA. SIA is
made LOW and now the second
empty location reaches the input
stage of FIFOA, after which DIRA
remains HIGH (11).
Sequence 3 (FIFOA runs full)
When 65 words are shifted in, DORA
remains HIGH due to valid data
remaining at the output of FIFOA. QnA
remains HIGH, being the polarity of
the 65th data word (6). After the 128th
SI pulse, DIR remains LOW and both
FIFOs are full (7). Additional pulses
have no effect.
Sequence 6 (FIFOB runs empty)
After the next SOB pulse, DIRB
remains HIGH due to the input stage
of FIFOB being empty. After another
63 SOB pulses, DORB remains LOW
due to both FIFOs being empty (14).
Additional SOB pulses have no effect.
The last word remains available at the
output Qn.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic
Package Outlines”.
September 1993
28
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