74LV273PW,118 [NXP]
74LV273 - Octal D-type flip-flop with reset; positive-edge trigger TSSOP2 20-Pin;
| 型号： | 74LV273PW,118 |
| 厂家： | 
NXP |
| 描述： | 74LV273 - Octal D-type flip-flop with reset; positive-edge trigger TSSOP2 20-Pin 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LV273
Octal D-type flip-flop with reset;
positive-edge trigger
Product specification
1998 May 29
Supersedes data of 1997 Apr 07
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
74LV273
Octal D-type flip-flop with reset; positive edge-trigger
FEATURES
• Wide operating voltage: 1.0 to 5.5V
• Optimized for Low Voltage applications: 1.0 to 3.6V
DESCRIPTION
The 74LV273 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT273.
The 74LV273 has eight edge-triggered , D-type flip-flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip-flops
simultaneously. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
• Accepts TTL input levels between V = 2.7V and V = 3.6V
CC
CC
• Typical V
(output ground bounce) t 0.8V @ V = 3.3V,
OLP
CC
T
= 25°C
amb
• Typical V
(output V undershoot) u 2V @ V = 3.3V,
OHV
OH
CC
T
= 25°C
amb
All outputs will be forced LOW independently of clock or data inputs
by a LOW voltage level on the MR input.
• Ideal buffer for MOS microprocessor or memory
• Common clock and master reset
• Output capability: standard
The device is useful for applications where the true output only is
required and the clock and master reset are common to all storage
elements.
• I category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t =t v2.5 ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
12
13
C = 15pF
CP to Q
t
f
/t
ns
L
n;
PHL PLH
V
CC
= 3.3V
MR to Q
n
Maximum clock frequency
Input capacitance
110
3.5
20
MHz
pF
max
C
C
I
Power dissipation capacitance per flip-flop
Notes 1 and 2
pF
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C V
x f )S (C V
f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacitance in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
S (C V
f ) = sum of the outputs.
L
CC
o
2. The condition is V = GND to V
I
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LV273 N
PKG. DWG. #
SOT146-1
SOT163-1
SOT339-1
SOT360-1
20-Pin Plastic DIL
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
74LV273 N
74LV273 D
20-Pin Plastic SO
74LV273 D
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP
74LV273 DB
74LV273 PW
74LV273 DB
74LV273PW DH
2
1998 May 29
853–1965 19466
Philips Semiconductors
Product specification
74LV273
Octal D-type flip-flop with reset; positive edge-trigger
PIN CONFIGURATION
LOGIC SYMBOL
11
CP
20
19
18
17
16
15
14
13
12
11
V
CC
MR
1
2
3
4
5
6
7
8
9
3
D
D
D
D
D
D
D
D
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
2
5
0
1
2
3
4
5
6
7
Q
Q
0
0
1
7
7
6
4
D
D
D
D
7
6
8
9
Q
Q
1
2
2
3
6
5
5
4
13
14
17
18
12
15
16
19
Q
Q
D
D
D
D
Q
3
Q
4
MR
1
GND 10
CP
SV00366
SV00367
PIN DESCRIPTION
LOGIC SYMBOL (IEEE/IEC)
PIN
NUMBER
SYMBOL
FUNCTION
1
MR
Master reset input (active-LOW)
Flip-flop outputs
2, 5, 6, 9, 12,
15, 16, 19
Q to Q
0
7
11
C1
3, 4, 7, 8, 13,
14, 17, 18
1
R
D to D
Data inputs
Ground (0V)
0
7
10
11
20
GND
CP
2
5
3
1D
4
Clock input (LOW-to-HIGH, edge-
triggered)
7
6
V
CC
Positive supply voltage
8
9
13
14
17
18
12
15
16
19
SV00368
3
1998 May 29
Philips Semiconductors
Product specification
74LV273
Octal D-type flip-flop with reset; positive edge-trigger
FUNCTIONAL DIAGRAM
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODES
MR
L
CP
X
D
Q to Q
0
n
7
Reset (clear)
Load (‘1’)
X
L
H
L
3
4
7
D
D
D
Q
0
Q
1
Q
2
2
5
0
1
2
H
↑
h
l
Load (‘0’)
H
↑
6
H
h
=
=
HIGH voltage level
HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
LOW voltage level
LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
LOW–to–HIGH clock transition
Don’t care
8
13
14
17
18
D
D
D
D
D
Q
Q
Q
Q
Q
9
3
4
3
4
FF0
to
FF7
L
l
=
=
12
15
16
19
5
6
5
6
↑
X
=
=
7
7
1
MR
CP
11
SV00369
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
1.0
0
TYP.
3.3
–
MAX
UNIT
V
CC
DC supply voltage
See Note1
5.5
V
V
V
V
I
Input voltage
V
CC
CC
V
O
Output voltage
0
–
V
Operating ambient temperature range in free
air
See DC and AC
characteristics
–40
–40
+85
+125
T
amb
°C
V
CC
V
CC
V
CC
V
CC
= 1.0V to 2.0V
= 2.0V to 2.7V
= 2.7V to 3.6V
= 3.6V to 5.5V
–
–
–
–
500
200
100
50
–
–
–
t , t
r
Input rise and fall times
ns/V
f
NOTES:
1. The LV is guaranteed to function down to V = 1.0V (input levels GND or V ); DC characteristics are guaranteed from V = 1.2V to V = 5.5V.
CC
CC
CC
CC
4
1998 May 29
Philips Semiconductors
Product specification
74LV273
Octal D-type flip-flop with reset; positive edge-trigger
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
–0.5 to +7.0
±I
DC input diode current
DC output diode current
V < –0.5 or V > V + 0.5V
20
50
mA
mA
IK
I
I
CC
±I
OK
V
O
< –0.5 or V > V + 0.5V
O
CC
DC output source or sink current
– standard outputs
±I
O
–0.5V < V < V + 0.5V
mA
O
CC
25
DC V or GND current for types with
–standard outputs
CC
±I
±I
,
mA
GND
50
CC
T
stg
Storage temperature range
–65 to +150
°C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
P
TOT
mW
–plastic shrink mini-pack (SSOP and TSSOP)
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
-40°C to +85°C
-40°C to +125°C
SYMBOL
PARAMETER
TEST CONDITIONS
= 1.2V
UNIT
1
MIN
0.9
1.4
2.0
TYP
MAX
MIN
0.9
1.4
2.0
MAX
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 2.0V
HIGH level Input
voltage
V
IH
V
= 2.7 to 3.6V
= 4.5 to 5.5V
= 1.2V
0.7*V
0.7*V
CC
CC
0.3
0.6
0.8
0.3
0.6
0.8
= 2.0V
LOW level Input
voltage
V
IL
V
= 2.7 to 3.6V
= 4.5 to 5.5
0.3*V
0.3*V
CC
CC
= 1.2V; V = V or V –I = 100µA
1.2
2.0
2.7
3.0
4.5
I
IH
IL;
O
= 2.0V; V = V or V –I = 100µA
1.8
2.5
2.8
4.3
1.8
2.5
2.8
4.3
I
IH
IL;
O
HIGH level output
voltage; all outputs
= 2.7V; V = V or V –I = 100µA
V
V
V
V
I
IH
IL;
O
= 3.0V; V = V or V –I = 100µA
I
IH
IL;
O
V
OH
= 4.5V;V = V or V –I = 100µA
I
IH
IL;
O
HIGH level output
voltage;
STANDARD
V
V
= 3.0V;V = V or V –I = 6mA
2.40
3.60
2.82
4.20
2.20
3.50
CC
I
IH
IL;
O
= 4.5V;V = V or V –I = 12mA
CC
I
IH
IL;
O
outputs
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V; V = V or V I
IL; O
= 100µA
= 100µA
= 100µA
0
0
0
0
0
I
IH
= 2.0V; V = V or V
I
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
I
IH
IL; O
LOW level output
voltage; all outputs
= 2.7V; V = V or V
I
I
IH
IL; O
= 3.0V;V = V or V I
= 100µA
I = 100µA
I
IH
IL; O
V
OL
= 4.5V;V = V or V
IL; O
I
IH
LOW level output
voltage;
STANDARD
V
= 3.0V;V = V or V I = 6mA
IL; O
0.25
0.35
0.40
0.55
0.50
0.65
CC
CC
I
IH
V
= 4.5V;V = V or V I = 12mA
IL; O
I
IH
outputs
5
1998 May 29
Philips Semiconductors
Product specification
74LV273
Octal D-type flip-flop with reset; positive edge-trigger
DC CHARACTERISTICS FOR THE LV FAMILY (Continued)
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
= 5.5V; V = V or GND
UNIT
-40°C to +85°C
-40°C to +125°C
1.0
Input leakage
current
I
I
V
V
1.0
µA
µA
CC
I
CC
Quiescent supply
current; MSI
I
= 5.5V; V = V or GND; I = 0
20.0
160
850
CC
CC
I
CC
O
Additional
quiescent supply
current per input
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V
500
µA
I
CC
NOTE:
1. All typical values are measured at T
= 25°C.
amb
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF; R = 1KΩ
r
f
L
L
LIMITS
–40 to +85 °C
LIMITS
–40 to +125 °C
CONDITION
(V)
SYMBOL
PARAMETER
WAVEFORM
UNIT
1
V
CC
MIN
–
TYP
MAX
–
MIN
–
MAX
–
1.2
2.0
2.7
75
26
19
–
32
24
19
16
–
–
41
30
24
20
–
Propagation delay
CP to Q
–
–
t
t
Figure 1
Figure 2
ns
PHL/ PLH
n
2
3.0 to 3.6
4.5 to 5.5
1.2
–
14
–
–
–
–
–
80
27
20
–
2.0
–
44
33
26
22
–
–
56
41
33
28
–
Propagation delay
MR to Q
2.7
–
–
t
ns
PHL
n
2
3.0 to 3.6
4.5 to 5.5
2.0
–
15
–
–
–
9
6
–
34
25
20
34
25
20
–
41
30
24
41
30
24
–
Clock pulse width
2.7
–
–
t
t
Figure 1
Figure 2
ns
ns
W
2
3.0 to 3.6
2.0
5
–
–
10
8
–
–
Master reset pulse
width LOW
2.7
–
–
W
2
3.0 to 3.6
1.2
6
–
–
–10
–4
–
–
2.0
5
–
5
–
Removal time
MR to CP
t
Figure 2
Figure 3
ns
ns
rem
2.7
5
–3
–
5
–
2
3.0 to 3.6
1.2
5
–2
–
5
–
–
20
7
–
–
–
2.0
22
16
13
–
–
26
19
15
–
–
Set-up time
D to CP
n
t
su
2.7
5
–
–
2
3.0 to 3.6
1.2
4
–
–
–10
–4
–
–
2.0
5
–
5
–
Hold time
D to CP
n
t
h
Figure 3
Figure 1
ns
2.7
5
–3
–
5
–
2
3.0 to 3.6
2.0
5
–2
–
5
–
14
19
24
40
75
–
12
16
20
–
Maximum clock
pulse frequency
2.7
–
–
f
MHz
max
2
3.0 to 3.6
100
–
–
NOTE:
1. Unless otherwise stated, all typical values are at T
= 25°C.
amb
2. Typical value measured at V = 3.3V.
CC
3. Typical value measured at V = 5.0V.
CC
6
1998 May 29
Philips Semiconductors
Product specification
74LV273
Octal D-type flip-flop with reset; positive edge-trigger
AC WAVEFORMS
V
V
V
= 1.5V at V w 2.7V v 3.6V
M
CC
= 0.5V * V at V t 2.7V and w 4.5V
M
CC
CC
and V are the typical output voltage drop that occur with the
OL
OH
output load.
V
I
CP INPUT
GND
V
M
t
t
su
su
t
h
t
h
V
I
1/f
MAX
D
INPUT
GND
V
n
M
V
I
CP INPUT
GND
V
M
V
OH
t
w
t
t
PLH
PHL
Q
n
OUTPUT
V
M
V
OH
V
OL
Qn OUTPUT
V
M
V
OL
SV00371
Figure 3. Data set-up and hold times for the data input (D )
n
NOTE:
SV00370
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Figure 1. The clock (CP) to output (Q ) propagation delays, the
n
clock pulse width and the maximum clock pulse frequency
TEST CIRCUIT
V
cc
V
V
O
l
PULSE
GENERATOR
V
I
D.U.T.
50pF
MR INPUT
GND
V
M
V
M
R = 1k
L
R
T
C
L
t
t
rem
w
V
I
Test Circuit for Outputs
CP INPUT
GND
V
M
DEFINITIONS
R
L
C
L
R
T
= Load resistor
t
PHL
V
OH
= Load capacitance includes jig and probe capacitiance
= Termination resistance should be equal to Z of pulse generators.
Qn OUTPUT
V
OUT
M
V
OL
TEST
V
V
I
CC
t
t
< 2.7V
2.7–3.6V
≥ 4.5 V
V
CC
PLH/ PHL
2.7V
V
CC
SV00372
SV00902
Figure 4. Load circuitry for switching times
Figure 2. The master reset (MR) pulse width, the master reset
to output (Q ) propagations delay and the master reset to clock
n
(CP) removal time
7
1998 May 29
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1998 May 29
8
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1998 May 29
9
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
1998 May 29
10
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
1998 May 29
11
Philips Semiconductors
Product specification
Octal D–type flip–flop with reset; positive edge–trigger
74LV273
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04443
Document order number:
Philips
Semiconductors
相关型号：
74LV273PW-T
IC LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, FF/Latch
NXP
74LV273PWDH-T
IC LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, FF/Latch
NXP
©2020 ICPDF网 联系我们和版权申明