74LV373PWDH [NXP]
Octal D-type transparent latch 3-State; 八D型透明锁存器3 -STATE
| 型号： | 74LV373PWDH |
| 厂家： | 
NXP |
| 描述： | Octal D-type transparent latch 3-State |
| 文件： | 总12页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LV373
Octal D-type transparent latch (3-State)
Product specification
1998 Jun 10
Supersedes data of 1997 March 04
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
FEATURES
• Wide operating voltage: 1.0 to 5.5V
DESCRIPTION
The 74LV373 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT373.
• Optimized for Low Voltage applications: 1.0V to 3.6V
The 74LV373 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
• Accepts TTL input levels between V = 2.7V and V = 3.6V
CC
CC
• Typical V
(output ground bounce) < 0.8V at V = 3.3V,
OLP
= 25°C
CC
T
amb
The ‘373’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
• Typical V
(output V undershoot) > 2V at V = 3.3V,
OHV
= 25°C
OH
CC
T
amb
• Common 3-State output enable input
• Output capability: bus driver
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
• I category: MSI
CC
The ‘373’ is functionally identical to the ‘573’, but the ‘573’ has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t = t v2.5 ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
D to Q
C = 15pF
L
V
CC
= 3.3V
10
12
t
/t
ns
n
n
PHL PLH
LE to Q
n
C
C
Input capacitance
3.5
22
pF
pF
I
Power dissipation capacitance per latch
Notes 1, 2
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C V
x f )ȍ (C V
f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
ȍ (C V
f ) = sum of the outputs.
L
CC
o
2. The condition is V = GND to V
I
CC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
20-Pin Plastic DIL
TEMPERATURE RANGE
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV373 N
NORTH AMERICA
74LV373 N
PKG. DWG. #
SOT146-1
SOT163-1
SOT339-1
SOT360-1
20-Pin Plastic SO
–40°C to +125°C
74LV373 D
74LV373 D
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
–40°C to +125°C
74LV373 DB
74LV373 DB
–40°C to +125°C
74LV373 PW
74LV373PW DH
PIN DESCRIPTION
PIN NUMBER SYMBOL
FUNCTION
1
OE
Q –Q
Output enabled input (active LOW)
2, 5, 6, 9, 12,
15, 16, 19
3-State latch outputs
Data inputs
0
7
3, 4, 7, 8, 13,
14, 17, 18
D –D
0
7
10
11
20
GND
LE
Ground (0V)
Latch enable input (active HIGH)
Positive supply voltage
V
CC
2
1998 Jun 10
853–1934 19545
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
PIN CONFIGURATION
LOGIC SYMBOL
11
1
2
3
4
5
6
7
8
9
20
19
V
OE
CC
Q
Q
0
7
LE
3
4
D
D
D
D
D
D
D
D
2
5
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
0
1
2
3
4
5
6
7
D
0
18
17
16
15
14
13
12
D
D
Q
Q
D
D
Q
7
6
6
5
5
D
1
6
7
Q
1
8
9
Q
2
12
15
16
19
13
14
17
18
D
2
D
3
4
4
Q
3
OE
GND 10
11 LE
1
SV00658
SV00657
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
11
C1
3
4
7
8
D
D
D
D
2
5
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
0
1
2
3
4
1
EN1
6
3
2
1D
9
4
7
5
LATCH
1 to 8
3–STATE
OUTPUTS
12
13
14
17
18
D
D
D
D
4
5
6
7
6
15
16
19
5
6
7
8
9
12
13
14
17
18
15
16
19
11
1
LE
OE
SV00659
SV00660
LOGIC DIAGRAM
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00661
3
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
FUNCTION TABLE
INPUTS
OUTPUTS
INTERNAL
LATCHES
OPERATING MODES
OE
LE
Dn
Q to Q
0
7
Enable and read register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
L
L
L
L
I
h
L
H
L
H
Latch and read register
H
H
L
L
I
h
L
H
Z
Z
Latch register and disable outputs
= HIGH voltage level
H
h
L
I
X
Z
= HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
= LOW voltage level
= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
= Don’t care
= High impedance OFF-state
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP.
3.3
–
MAX
UNIT
V
CC
DC supply voltage
See Note1
1.0
0
5.5
V
V
V
V
I
Input voltage
V
CC
V
CC
V
O
Output voltage
0
–
Operating ambient temperature range in free
air
See DC and AC
characteristics
–40
–40
+85
+125
T
amb
°C
V
CC
V
CC
V
CC
V
CC
= 1.0V to 2.0V
= 2.0V to 2.7V
= 2.7V to 3.6V
= 3.6V to 5.5V
–
–
–
–
–
–
–
–
500
200
100
50
t , t
r
Input rise and fall times
ns/V
f
NOTE:
1. The LV is guaranteed to function down to V = 1.0V (input levels GND or V ); DC characteristics are guaranteed from V = 1.2V to V = 5.5V.
CC
CC
CC
CC
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
20
UNIT
V
CC
V
±I
IK
DC input diode current
DC output diode current
V < –0.5 or V > V + 0.5V
mA
mA
I
I
CC
±I
OK
V
O
< –0.5 or V > V + 0.5V
50
O
CC
DC output source or sink current
– bus driver outputs
±I
O
–0.5V < V < V + 0.5V
35
mA
O
CC
DC V or GND current for types with
–bus driver outputs
CC
±I
±I
,
70
mA
GND
CC
T
stg
Storage temperature range
–65 to +150
°C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
P
tot
mW
–plastic shrink mini-pack (SSOP and TSSOP)
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
DC CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
MAX
-40°C to +85°C
-40°C to +125°C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
1
MIN
0.9
1.4
2.0
TYP
MIN
0.9
1.4
2.0
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
= 2.0V
HIGH level Input
voltage
V
IH
V
= 2.7 to 3.6V
= 4.5 to 5.5V
= 1.2V
0.7*V
0.7*V
CC
CC
0.3
0.6
0.8
0.3
0.6
0.8
= 2.0V
LOW level Input
voltage
V
IL
V
V
= 2.7 to 3.6V
= 4.5 to 5.5
0.3*V
0.3*V
CC
CC
= 1.2V; V = V or V –I = 100µA
1.2
2.0
2.7
3.0
4.5
I
IH
IL;
O
= 2.0V; V = V or V –I = 100µA
1.8
2.5
2.8
4.3
1.8
2.5
2.8
4.3
I
IH
IL;
O
HIGH level output
voltage; all outputs
= 2.7V; V = V or V –I = 100µA
I
IH
IL;
O
= 3.0V; V = V or V –I = 100µA
I
IH
IL;
O
V
OH
= 4.5V; V = V or V –I = 100µA
I
IH
IL;
O
HIGH level output
voltage; BUS driver
outputs
V
CC
V
CC
= 3.0V; V = V or V –I = 8mA
2.40
3.60
2.82
4.20
2.20
3.50
I
IH
IL;
O
= 4.5V; V = V or V –I = 16mA
I
IH
IL;
O
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V; V = V or V I
IL; O
= 100µA
= 100µA
= 100µA
= 100µA
= 100µA
0
0
0
0
0
I
IH
= 2.0V; V = V or V I
IL; O
0.2
0.2
0.2
0.2
0.2
I
IH
LOW level output
= 2.7V; V = V or V I
IL; O
0.2
0.2
0.2
I
IH
= 3.0V; V = V or V I
IL; O
I
IH
V
OL
V
= 4.5V; V = V or V I
IL; O
I
IH
LOW level output
voltage; BUS driver
outputs
V
= 3.0V; V = V or V
I
= 8mA
0.20
0.35
0.40
0.55
0.50
0.65
CC
CC
I
IH
IL; O
V
= 4.5V; V = V or V
I
= 16mA
I
IH
IL; O
Input leakage
current
I
V
= 5.5V; V = V or GND
1.0
5
1.0
10
µA
µA
µA
I
CC
I
CC
3-State output
OFF-state current
V
V
= 5.5V; V = V or V
I IH IL;
CC
O
I
OZ
CC
= V or GND
CC
Quiescent supply
current; MSI
I
V
CC
= 5.5V; V = V or GND; I = 0
20.0
160
I
CC
O
Additional
quiescent supply
current per input
∆I
CC
V
CC
= 2.7V to 3.6V; V = V – 0.6V
500
850
µA
I
CC
NOTE:
1. All typical values are measured at T
= 25°C.
amb
5
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
AC CHARACTERISTICS
GND = 0V; t = t ≤ 2.5ns; C = 50pF; R = 1KW
r
f
L
L
LIMITS
–40 to +85 °C
CONDITION
(V)
SYMBOL
PARAMETER
WAVEFORM
UNIT
–40 to +125 °C
1
V
CC
MIN
–
TYP
MAX
–
MIN
–
MAX
–
1.2
2.0
2.7
65
–
22
37
28
22
16
–
–
48
35
28
20
–
Propagation delay
D to Q
t
t
Figure 1, 5
Figure 2, 5
Figure 3
ns
–
16
–
PHL/ PLH
n
n
2
3.0 to 3.6
4.5 to 5.5
1.2
–
13
–
–
–
–
–
80
27
20
–
2.0
–
43
26
25
19
–
–
54
33
31
24
–
Propagation delay
LE to Q
t
t
ns
ns
ns
2.7
–
–
PHL/ PLH
n
2
3.0 to 3.6
4.5 to 5.5
1.2
–
15
–
3
–
9.5
–
–
80
27
20
–
2.0
–
46
28
27
23
–
–
58
35
34
29
–
3-State output
enable time
t
t
t
2.7
–
–
PZH/ PZL
OE to Q
n
2
3.0 to 3.6
4.5 to 5.5
1.2
–
15
–
–
–
–
–
75
27
21
–
2.0
–
46
28
27
23
–
–
58
35
34
29
–
3-State output
disable time
t
Figure 3
2.7
–
–
PHZ/ PLZ
OE to Q
n
2
3.0 to 3.6
4.5 to 5.5
2.0
–
16
–
–
–
–
34
25
20
–
10
8
41
30
24
–
t
W
LE pulse width HIGH
Figure 2
Figure 4
ns
ns
2.7
–
–
2
3.0 to 3.6
1.2
6
–
–
25
9
–
–
2.0
17
13
10
–
–
20
15
12
–
–
t
su
Setup time D to LE
n
2.7
6
–
–
2
3.0 to 3.6
1.2
5
–
–
–15
–5
–
–
2.0
5
–
5
–
t
h
Hold time D to LE
Figure 4
ns
n
2.7
5
–3
–
5
–
2
3.0 to 3.6
5
–3
–
5
–
NOTES:
1. All typical values are measured at T
= 25°C
amb
2. Typical values are measured at V = 3.3V
CC
3. Typical values are measured at V = 5.0V
CC
6
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
AC WAVEFORMS
V
V
V
= 1.5V at V w 2.7V and v 3.6V
M
CC
V
I
= 0.5V * V at V t 2.7V and w 4.5V
M
CC
CC
and V are the typical output voltage drop that occur with the
OL
OH
D
INPUT
V
n
M
output load.
V
X
V
X
V
Y
V
Y
= V + 0.3V at V w 2.7V and v 3.6V
GND
OL CC
t
h
t
h
= V + 0.1V at V < 2.7V and w 4.5V
OL
CC
CC
= V – 0.3V at V w 2.7V and v 3.6V
OH
CC
t
su
t
su
= V – 0.1V at V < 2.7V and w 4.5V
OH
CC
CC
V
I
V
LE INPUT
GND
I
V
M
D
n
INPUT
GND
V
M
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SV00665
t
t
PLH
PHL
Figure 4. Data set-up and hold times
for the D input to the LE input.
V
OH
n
Q
n
OUTPUT
V
M
V
TEST CIRCUIT
OL
SV00662
Figure 1. Data input (D ) to output (Q ) propagation delays and
n
n
V
CC
2 * V
the output transition times.
CC
Open
GND
R
R
= 1k
L
L
V
V
O
V
I
I
PULSE
GENERATOR
D.U.T.
LE INPUT
GND
V
M
t
= 1k
R
T
50 pF
C
L
t
W
t
PHL
PLH
Test Circuit for Outputs
V
OH
Q
n
OUTPUT
DEFINITIONS
V
M
R
C
R
= Load resistor
L
L
T
V
= Load capacitance includes jig and probe capacitiance.
= Termination resistance should be equal to Z
OL
of pulse generators.
OUT
SV00663
SWITCH POSITION
Figure 2. Latch enable input (LE) pulse width, the latch enable
input to output (Q ) propagation delays
S
n
TEST
V
V
I
1
CC
and the output transition times.
t
t
Open
2 * V
< 2.7V
V
CC
PLH/ PHL
t
t
t
2.7V
PLZ/ PZL
CC
2.7–3.6V
V
I
V
w 4.5V
CC
t
GND
PHZ/ PZH
V
OE INPUT
GND
M
SV00896
Figure 5. Load circuitry for switching times
t
t
PZL
PLZ
V
CC
Q
OUTPUT
n
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
PZH
t
PHZ
V
OH
V
Y
Q
n
OUTPUT
V
M
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
disabled
outputs
enabled
outputs
enabled
SV00664
Figure 3. 3-State enable and disable times.
7
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
8
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
9
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
10
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
11
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV373
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04447
Document order number:
Philips
Semiconductors
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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