74LV374D,118 [NXP]
74LV374 - Octal D-type flip-flop; positive edge-trigger; 3-state SOP 20-Pin;
| 型号： | 74LV374D,118 |
| 厂家： | 
NXP |
| 描述： | 74LV374 - Octal D-type flip-flop; positive edge-trigger; 3-state SOP 20-Pin 驱动 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总17页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LV374
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 02 — 14 May 2009
Product data sheet
1. General description
The 74LV374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop
and 3-state outputs for bus-oriented applications. A clock input (CP) and an output enable
input (OE) are common to all flip-flops. The 74LV374 is a low-voltage Si-gate CMOS
device and is pin and function compatible with 74HC374 and 74HCT374.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
2. Features
I Wide operating voltage: 1.0 V to 5.5 V
I Optimized for low voltage applications: 1.0 V to 3.6 V
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 °C
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Common 3-state output enable input
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74LV374N
74LV374D
−40 °C to +125 °C
−40 °C to +125 °C
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74LV374DB −40 °C to +125 °C
SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74LV374PW −40 °C to +125 °C
TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
4. Functional diagram
1
EN
11
C1
11
3
2
1D
CP
3
2
5
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
5
6
9
4
7
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
OE
1
mna196
mna891
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Q0
Q1
Q2
Q3
3
4
2
5
6
9
D0
D1
D2
D3
D4
7
8
FF1
to
FF8
3-STATE
OUTPUTS
13
Q4 12
Q5
14 D5
15
17
18
Q6 16
Q7 19
D6
D7
CP
OE
11
1
mna892
Fig 3. Functional diagram
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
2 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Fig 4. Logic diagram
5. Pinning information
5.1 Pinning
74LV374
74LV374
1
2
20
1
2
20
19
18
17
16
15
14
13
12
11
OE
Q0
V
OE
V
CC
CC
19
18
17
16
15
14
13
12
11
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
3
3
D0
4
4
D1
5
5
Q1
6
6
Q2
7
7
D2
8
8
D3
9
9
Q3
10
10
GND
GND
001aak107
001aak108
Fig 5. Pin configuration DIP20, SO20
Fig 6. Pin configuration SSOP20, TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
output enable input (active LOW)
data output
Q0 to Q7
D0 to D7
GND
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
data input
10
11
20
ground (0 V)
CP
clock input (LOW to HIGH; edge triggered)
supply voltage
VCC
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
3 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
OE
L
Internal flip-flop Output
CP
↑
Dn
Qn
L
Load and read register
l
L
L
↑
h
l
H
L
H
Z
Load register and disable
outputs
H
↑
H
↑
h
H
Z
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
↑ = LOW to HIGH clock transition
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
±20
±50
±35
70
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
-
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−70
−65
-
storage temperature
total power dissipation
+150
[2]
Tamb = −40 °C to +125 °C
DIP20
-
-
750
500
mW
mW
SO20, SSOP20 and TSSOP20
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP20 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
4 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
Parameter
supply voltage[1]
Conditions
Min
Typ
Max
5.5
Unit
V
1.0
3.3
VI
input voltage
0
-
VCC
VCC
+125
500
200
100
50
V
VO
output voltage
0
-
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
+25
°C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input voltage
VCC = 1.2 V
0.9
-
-
-
-
-
-
-
-
-
0.9
-
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.4
-
-
1.4
-
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
2.0
2.0
0.7VCC
-
0.7VCC
-
VIL
LOW-level input voltage
HIGH-level output voltage
-
-
-
-
0.3
0.6
0.8
0.3VCC
-
-
-
-
0.3
0.6
0.8
0.3VCC
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
VOH
IO = −100 µA; VCC = 1.2 V
IO = −100 µA; VCC = 2.0 V
IO = −100 µA; VCC = 2.7 V
IO = −100 µA; VCC = 3.0 V
IO = −100 µA; VCC = 4.5 V
IO = −8 mA; VCC = 3.0 V
IO = −16 mA; VCC = 4.5 V
-
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
1.8
2.5
2.8
4.3
2.4
3.6
1.8
2.5
2.8
4.3
2.2
3.5
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
5 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 100 µA; VCC = 1.2 V
IO = 100 µA; VCC = 2.0 V
IO = 100 µA; VCC = 2.7 V
IO = 100 µA; VCC = 3.0 V
IO = 100 µA; VCC = 4.5 V
IO = 8 mA; VCC = 3.0 V
IO = 16 mA; VCC = 4.5 V
VI = VCC or GND;
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
V
0.2
0.2
0.2
0.2
0.40
0.55
1.0
0.2
0.2
0.2
0.2
0.50
0.65
1.0
V
0
V
0
V
0
V
0.20
0.35
-
V
V
II
input leakage current
µA
VCC = 5.5 V
IOZ
OFF-state output current
VI = VIH or VIL;
-
-
5
-
10
µA
VO = VCC or GND;
V
CC = 5.5 V
VI = VCC or GND; IO = 0 A;
CC = 5.5 V
per input; VI = VCC − 0.6 V;
CC = 2.7 V to 3.6 V
ICC
∆ICC
CI
supply current
-
-
-
-
-
20
500
-
-
-
-
160
850
-
µA
µA
pF
V
additional supply current
input capacitance
V
3.5
[1] Typical values are measured at Tamb = 25 °C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions −40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay CP to Qn; see Figure 7
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
-
-
-
-
-
-
90
31
23
14
17
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
39
29
-
49
36
-
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
OE to Qn; see Figure 8
VCC = 1.2 V
23
19
29
24
[4]
ten
enable time
-
-
-
-
-
75
26
19
14
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
34
25
20
17
43
31
25
21
VCC = 2.7 V
[3]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
6 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[5]
tdis
disable time
OE to Qn; Figure 8
VCC = 1.2 V
-
-
-
-
-
80
29
22
17
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
39
29
24
20
48
36
29
24
VCC = 2.7 V
[3]
[3]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CP, HIGH or LOW; see Figure 7
VCC = 2.0 V
tW
pulse width
set-up time
34
25
20
12
9
-
-
-
41
30
24
-
-
-
ns
ns
ns
VCC = 2.7 V
[3]
[3]
[3]
VCC = 3.0 V to 3.6 V
Dn to CP; see Figure 9
VCC = 1.2 V
7
tsu
-
25
9
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
22
16
13
26
19
15
VCC = 2.7 V
6
VCC = 3.0 V to 3.6 V
Dn to CP; see Figure 9
VCC = 1.2 V
5
th
hold time
-
−10
−3
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
5
5
5
5
5
5
VCC = 2.7 V
−2
VCC = 3.0 V to 3.6 V
see Figure 7
−2
fmax
maximum
frequency
VCC = 2.0 V
15
19
-
40
58
77
70
25
-
-
-
-
12
16
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 2.7 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
[3]
[6]
24
20
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
[3] Typical value measured at VCC = 3.3 V.
[4] ten is the same as tPZH and tPZL
[5] tdis is the same as tPHZ and tPLZ
.
.
.
[6] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
7 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
11. Waveforms
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
mna894
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The clock (CP) to output (Qn) propagation delays, the clock (CP) pulse width and the maximum
clock pulse frequency
V
I
OE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna644
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Enable and disable times
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
8 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
M
Dn input
GND
V
OH
V
Qn output
M
V
OL
mna202
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. The data set-up and hold times for the Dn input to the CP input
Table 8.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
Vx
Vy
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
V
V
V
OH − 0.3 V
2.7 V to 3.6 V
≥ 4.5 V
OH − 0.3 V
OH − 0.3 V
0.5VCC
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
9 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage Input
Load
CL
VEXT
VCC
VI
tr, tf
RL
tPHL, tPLH
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCC
< 2.7 V
VCC
2.7 V
VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
50 pF
1 kΩ
2.7 V to 3.6 V
≥ 4.5 V
15 pF, 50 pF 1 kΩ
50 pF 1 kΩ
open
GND
2VCC
open
GND
2VCC
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
10 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
12. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 11. Package outline SOT146-1 (DIP20)
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
11 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 12. Package outline SOT163-1 (SO20)
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
12 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 13. Package outline SOT339-1 (SSOP20)
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
13 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 14. Package outline SOT360-1 (TSSOP20)
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
14 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
DUT
Description
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74LV374_2
Modifications:
Release date
20090514
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV374_1
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Quick reference data removed
• Added type number 74LV374PW (TSSOP20 package)
74LV374_1
19970320
Product specification
-
-
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
15 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LV374_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 14 May 2009
16 of 17
74LV374
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 May 2009
Document identifier: 74LV374_2
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