74LV377D [NXP]
Octal D-type flip-flop with data enable; positive edge-trigger; 八路D型触发器与数据使能;正边沿触发
| 型号： | 74LV377D |
| 厂家： | 
NXP |
| 描述： | Octal D-type flip-flop with data enable; positive edge-trigger |
| 文件： | 总12页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
Product specification
1998 Jun 10
Supersedes data of 1997 Mar 04
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
FEATURES
DESCRIPTION
The 74LV377 is a low–voltage CMOS device and is pin and function
compatible with 74HC/HCT377.
• Optimized for Low Voltage applications: 1.0 to 3.6V
• Accepts TTL input levels between V = 2.7V and V = 3.6V
CC
CC
The 74LV377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH
• Typical V
(output ground bounce) t 0.8V @ V = 3.3V,
OLP
CC
T
= 25°C
amb
• Typical V
(output V undershoot) u 2V @ V = 3.3V,
OHV
OH
CC
clock transition, is transferred to the corresponding output (Q ) of
n
T
= 25°C
amb
the flip-flop. The E input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
• Ideal for addressable register applications
• Data enable for address and data synchronization applications
• Eight positive-edge triggered D-type flip-flops
• Output capability: standard
• I category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t = t v2.5 ns
amb
r f
SYMBOL
PARAMETER
Propagation delay
CONDITIONS
TYPICAL
UNIT
t
f
/t
13
ns
PHL PLH
CP to Q
C = 15pF
n
L
V
= 3.3V
CC
Maximum clock frequency
Input capacitance
77
3.5
20
MHz
pF
max
C
C
I
Power dissipation capacitance per flip-flop
Notes 1 and 2
pF
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C V
f )S (C V
f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
S (C V
f ) = sum of the outputs.
L
CC
o
2. The condition is V = GND to V
I
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LV377 N
PKG. DWG. #
SOT146-1
SOT163-1
SOT339-1
SOT360-1
20-Pin Plastic DIL
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
74LV377 N
74LV377 D
20-Pin Plastic SO
74LV377 D
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
74LV377 DB
74LV377 PW
74LV377 DB
74LV377PW DH
PIN DESCRIPTION
FUNCTION TABLE
INPUTS
OUTPUTS
PIN
SYMBOL
NUMBER
FUNCTION
OPERATING MODES
CP
↑
E
l
D
Q
n
n
1
E
Data enable input (active-LOW)
flip-flop outputs
Load ‘‘1’’
Load ‘‘0’’
h
H
2, 5, 6, 9, 12,
15, 16, 19
Q to Q
0
↑
l
l
L
7
↑
X
h
H
X
X
No change
No change
3, 4, 7, 8, 13,
14, 17, 18
Hold (do nothing)
D to D
Data inputs
Ground (0V)
0
7
H
h
=
=
HIGH voltage level
10
11
20
GND
HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
LOW voltage level
LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
LOW–to–HIGH CP transition
Don’t care
Clock input
(LOW-to-HIGH, edge-triggered)
CP
L
l
=
=
V
CC
Positive supply voltage
↑
X
=
=
2
1998 Jun 10
853–1935 19545
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
11
1C2
1
1
2
3
4
5
6
20
19
V
CC
E
G1
Q
7
Q
0
3
2
D
D
18
17
16
15
14
13
12
11
D
7
D
6
Q
6
Q
5
D
5
0
1
2D
4
7
8
5
6
Q
Q
D
1
2
9
7
8
2
12
13
14
17
18
D
D
Q
3
4
15
16
19
9
Q
3
4
10
GND
CP
SV00667
SV00669
LOGIC SYMBOL
FUNCTIONAL DIAGRAM
11
D
0
Q
Q
Q
Q
Q
0
1
2
3
4
3
2
5
CP
D
1
3
4
2
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
4
0
1
2
3
4
0
1
2
3
4
D
2
5
7
6
D
3
D
4
7
6
8
9
FF1
to
FF8
OUTPUTS
8
9
13
12
15
16
19
D
D
D
Q
5
Q
6
Q
7
5
6
7
13
12
14
17
18
14
17
18
D
D
D
15
16
19
5
6
7
5
6
7
E
E
1
CP
11
1
SV00668
SV00670
3
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
1.0
0
TYP
3.3
–
MAX
UNIT
V
CC
DC supply voltage
Input voltage
See Note 1
3.6
V
V
V
V
I
V
CC
V
CC
V
O
Output voltage
0
–
See DC and AC
characteristics
–40
–40
+85
+125
T
amb
Operating ambient temperature range in free air
°C
–
–
–
–
V
CC
V
CC
V
CC
= 1.0V to 2.0V
= 2.0V to 2.7V
= 2.7V to 3.6V
–
–
–
500
200
100
t , t
r
Input rise and fall times
ns/V
f
NOTE:
1. The LV is guaranteed to function down to V = 1.0V (input levels GND or V ); DC characteristics are guaranteed from V = 1.2V to V = 3.6V.
CC
CC
CC
CC
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +4.6
20
UNIT
V
CC
V
±I
IK
DC input diode current
DC output diode current
V < –0.5 or V > V + 0.5V
mA
mA
I
I
CC
±I
OK
V
O
< –0.5 or V > V + 0.5V
50
O
CC
DC output source or sink current
– standard outputs
±I
O
–0.5V < V < V + 0.5V
25
mA
O
CC
DC V or GND current for types with
–standard outputs
CC
±I
±I
,
50
mA
GND
CC
T
stg
Storage temperature range
–65 to +150
°C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
P
tot
mW
–plastic shrink mini-pack (SSOP and TSSOP)
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
MAX
-40°C to +85°C
-40°C to +125°C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
V
1
MIN
0.9
1.4
2.0
TYP
MIN
0.9
1.4
2.0
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
HIGH level Input
voltage
= 2.0V
V
IH
= 2.7 to 3.6V
= 1.2V
0.3
0.6
0.8
0.3
0.6
0.8
LOW level Input
voltage
= 2.0V
V
IL
V
= 2.7 to 3.6V
= 1.2V; V = V or V –I = 100µA
1.2
2.0
2.7
3.0
I
IH
IL;
O
= 2.0V; V = V or V –I = 100µA
1.8
2.5
2.8
1.8
2.5
2.8
I
IH
IL;
O
HIGH level output
voltage; all outputs
= 2.7V; V = V or V –I = 100µA
I
IH
IL;
O
= 3.0V; V = V or V –I = 100µA
V
OH
V
I
IH
IL;
O
HIGH level output
voltage;
STANDARD
outputs
V
CC
= 3.0V; V = V or V –I = 6mA
2.40
2.82
2.20
I
IH
IL;
O
V
CC
V
CC
V
CC
V
CC
= 1.2V; V = V or V I
IL; O
= 100µA
= 100µA
= 100µA
= 100µA
0
0
0
0
I
IH
= 2.0V; V = V or V I
IL; O
0.2
0.2
0.2
0.2
0.2
0.2
I
IH
LOW level output
voltage; all outputs
= 2.7V; V = V or V
I
I
IH
IL; O
= 3.0V; V = V or V
I
V
OL
V
I
IH
IL; O
LOW level output
voltage;
STANDARD
outputs
V
CC
= 3.0V; V = V or V I = 6mA
IL; O
0.25
0.40
0.50
I
IH
Input leakage
current
I
V
V
= 3.6V; V = V or GND
1.0
1.0
µA
µA
I
CC
I
CC
Quiescent supply
current; MSI
I
= 3.6V; V = V or GND; I = 0
20.0
160
CC
CC
I
CC
O
Additional
quiescent supply
current per input
∆I
CC
V
CC
= 2.7V to 3.6V; V = V – 0.6V
500
850
µA
I
CC
NOTE:
1. All typical values are measured at T
= 25°C.
amb
5
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
AC CHARACTERISTICS
GND = 0V; t = t ≤ 2.5ns; C = 50pF; R =1KW
r
f
L
L
LIMITS
–40 to +85 °C
CONDITION
(V)
–40 to +125 °C
SYMBOL
PARAMETER
WAVEFORM
UNIT
ns
1
V
CC
MIN
–
TYP
80
MAX
–
MIN
–
MAX
–
1.2
2.0
2.7
–
27
51
38
30
–
–
61
45
36
–
Propagation delay
CP to Q
t
t
Figure 1
Figure 2
Figure 2
PHL/ PLH
n
–
20
–
2
3.0 to 3.6
2.0
–
15
9
–
34
25
20
–
41
30
24
–
Clock pulse width
2.7
6
–
–
t
W
ns
2
3.0 to 3.6
1.2
5
–
–
25
9
–
–
2.0
22
16
13
–
–
26
19
15
–
–
Set-up time
D to CP
t
su
ns
n
2.7
6
–
–
2
3.0 to 3.6
1.2
5
–
–
10
4
–
–
2.0
22
16
13
–
–
26
19
15
–
–
Set-up time
E to CP
t
su
Figure 2
Figure 2
ns
ns
2.7
3
–
–
2
3.0 to 3.6
1.2
2
–
–
–15
–5
–
–
2.0
5
–
5
–
Hold time
D to CP
t
h
h
n
2.7
5
–4
–
5
–
2
3.0 to 3.6
1.2
5
–3
–
5
–
–
–5
–2
–2
–
–
–
2.0
5
–
5
–
Hold time
E to CP
t
Figure 2
Figure 1
ns
2.7
5
–
5
–
2
3.0 to 3.6
2.0
5
–1
–
5
–
14
19
24
40
58
–
12
16
20
–
Maximum clock
pulse frequency
2.7
–
–
f
MHz
max
2
3.0 to 3.6
70
–
–
NOTES:
1. Unless otherwise stated, all typical values are at T
= 25°C.
amb
2. Typical value measured at V = 3.3V.
CC
6
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
AC WAVEFORMS
TEST CIRCUIT
V
V
V
= 1.5V at V w 2.7V
M
CC
= 0.5V * V at V t 2.7V
V
M
CC
CC
CC
and V are the typical output voltage drop that occur with the
OL
OH
output load.
V
V
O
1/f
max
I
V
PULSE
GENERATOR
CC
D.U.T.
CP INPUT
GND
V
M
50pF
R
= 1k
L
R
T
C
L
t
W
t
t
PLH
PHL
Test Circuit for switching times
DEFINITIONS
V
OH
Q
n
OUTPUT
V
M
R
L
C
L
R
T
= Load resistor
= Load capacitance includes jig and probe capacitance
= Termination resistance should be equal to Z of pulse generators.
V
OL
OUT
SV00707
TEST
V
V
I
Figure 1. Clock (CP) to output (Q ) propagation delays,
CC
n
the clock pulse width and the maximum clock pulse frequency.
t
t
< 2.7V
V
CC
PLH/ PHL
2.7–3.6V
2.7V
V
CC
SV00901
E INPUT
GND
V
M
Figure 3. Load circuitry for switching times
t
t
t
h
h
t
t
su
su
V
CC
STABLE
D
INPUT
GND
V
n
M
t
su
tW
h
V
CC
CP INPUT
GND
V
M
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SV00671
Figure 2. Data set-up and hold times from the data input (Dn)
and from the enable input (E) to the clock (CP).
7
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
8
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
9
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
10
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
11
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04449
Document order number:
Philips
Semiconductors
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