74LV4053DB,112 [NXP]
74LV4053 - Triple single-pole double-throw analog switch SSOP1 16-Pin;
| 型号： | 74LV4053DB,112 |
| 厂家： | 
NXP |
| 描述： | 74LV4053 - Triple single-pole double-throw analog switch SSOP1 16-Pin 光电二极管 |
| 文件： | 总26页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LV4053
Triple single-pole double-throw analog switch
Rev. 04 — 10 August 2009
Product data sheet
1. General description
The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device
and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has
a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common
input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all
switches into the high-impedance OFF-state, independent of Sn.
VCC and GND are the supply voltage connections for the digital control inputs (Sn and E).
The VCC to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VCC as a positive limit and VEE as a negative limit. VCC − VEE may not
exceed 6 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND
(typically ground). VEE and VSS are the supply voltage connections for the switches.
2. Features
I Optimized for low-voltage applications: 1.0 V to 3.6 V
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
I Low ON resistance:
N 180 Ω (typical) at VCC − VEE = 2.0 V
N 100 Ω (typical) at VCC − VEE = 3.0 V
N 75 Ω (typical) at VCC − VEE = 4.5 V
I Logic level translation:
N To enable 3 V logic to communicate with ±3 V analog signals
I Typical ‘break before make’ built in
I ESD protection:
N HBM JESD22-A114-C exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LV4053N
74LV4053D
−40 °C to +125 °C
−40 °C to +125 °C
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74LV4053DB
74LV4053PW
74LV4053BQ
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SSOP16
plastic shrink small outline package; 16 leads; body
width 5.3 mm
SOT338-1
SOT403-1
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
DHVQFN16 plastic dual-in line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
4. Functional diagram
E
6
V
CC
16
13 1Y1
12 1Y0
14 1Z
LOGIC
LEVEL
CONVERSION
S1 11
DECODER
1
2
2Y1
2Y0
LOGIC
LEVEL
S2 10
CONVERSION
15 2Z
3
5
4
3Y1
LOGIC
LEVEL
CONVERSION
S3
9
3Y0
3Z
8
7
GND
V
EE
001aak341
Fig 1. Functional diagram
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
2 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
6
EN
11
10
9
S1
S2
S3
1Y0
1Y1
1Z
12
13
14
2
MUX/DMUX
11
14
#
#
#
0
1
12
13
×
0
1
0/1
2Y0
2Y1
2Z
1
10
15
2
1
15
5
3Y0
3Y1
3Z
9
4
5
3
3
6
E
4
001aae125
001aae126
Fig 2. Logic symbol
Fig 3. IEC logic symbol
Y
V
V
EE
CC
V
CC
V
CC
V
V
EE
CC
V
EE
Z
from
logic
001aad544
Fig 4. Schematic diagram (one switch)
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
3 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
5. Pinning information
5.1 Pinning
74LV4053
74LV4053
terminal 1
index area
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
3Z
V
CC
2Z
74LV4053
2
3
4
5
6
7
15
14
13
12
11
10
2Y0
3Y1
3Z
2Z
1Z
1Z
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
3Z
V
CC
1Y1
1Y0
S1
1Y1
1Y0
S1
2Z
1Z
3Y0
E
3Y0
E
1Y1
1Y0
S1
(1)
CC
V
3Y0
E
V
S2
EE
V
EE
S2
V
EE
S2
GND
S3
001aak343
GND
S3
001aak424
Transparent top view
001aak342
Fig 5. Pin configuration SOT38-4
and SOT109-1
Fig 6. Pin configuration
Fig 7. Pin configuration for
SOT763-1
SOT338-1 and SOT403-1
5.2 Pin description
Table 2.
Symbol
E
Pin description
Pin
Description
6
enable input (active LOW)
supply voltage
VEE
7
GND
8
ground supply voltage
select input
S1, S2, S3
1Y0, 2Y0, 3Y0
1Y1, 2Y1, 3Y1
1Z, 2Z, 3Z
VCC
11, 10, 9
12, 2, 5
13, 1, 3
14, 15, 4
16
independent input or output
independent input or output
common output or input
supply voltage
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
4 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
6. Functional description
Table 3.
Function table [1]
Inputs
Channel on
E
L
Sn
L
nY0 to nZ
nY1 to nZ
switches off
L
H
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
±20
±20
±25
Unit
V
[1]
[2]
[2]
[2]
supply voltage
−0.5
input clamping current
VI < −0.5 V or VI > VCC + 0.5 V
-
-
-
mA
mA
mA
ISK
switch clamping current VSW < −0.5 V or VSW > VCC + 0.5 V
ISW
switch current
VSW > −0.5 V or VSW < VCC + 0.5 V;
source or sink current
Tstg
Ptot
storage temperature
total power dissipation
−65
+150
°C
[3]
Tamb = −40 °C to +125 °C
DIP16 package
-
-
-
-
750
500
500
500
mW
mW
mW
mW
SO16 package
TSSOP16 package
DHVQFN16 package
[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE
.
[2] The minimum input voltage rating may be exceeded if the input current rating is observed.
[3] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
5 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
6
Unit
V
supply voltage
input voltage
see Figure 8
1
3.3
VI
0
-
-
-
-
-
-
VCC
VCC
+125
500
200
100
V
VSW
switch voltage
ambient temperature
0
V
Tamb
in free air
−40
°C
∆t/∆V
input transition rise and fall rate VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
-
-
-
ns/V
ns/V
ns/V
VCC = 2.7 V to 3.6 V
[1] The static characteristics are guaranteed from VCC = 1.2 V to 6.0 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with
input levels GND or VCC).
001aak344
8.0
- GND
V
CC
(V)
6.0
4.0
2.0
0
operating area
0
2.0
4.0
6.0
CC
8.0
- V (V)
V
EE
Fig 8. Guaranteed operating area as a function of the supply voltages
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
6 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input voltage
VCC = 1.2 V
0.9
-
-
-
-
-
-
-
-
-
-
-
-
0.9
-
-
V
V
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.4
1.4
VCC = 2.7 V to 3.6 V
VCC = 4.5 V
2.0
-
2.0
-
3.15
-
3.15
-
VCC = 6.0 V
4.20
-
4.20
-
VIL
LOW-level input voltage
input leakage current
VCC = 1.2 V
-
-
-
-
-
0.3
0.6
0.8
1.35
1.80
-
-
-
-
-
0.3
0.6
0.8
1.35
1.80
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V
VCC = 6.0 V
II
VI = VCC or GND
VCC = 3.6 V
-
-
-
-
1.0
2.0
-
-
1.0
2.0
µA
µA
VCC = 6.0 V
IS(OFF)
IS(ON)
ICC
OFF-state leakage current VI = VIH or VIL; see Figure 9
VCC = 3.6 V
VCC = 6.0 V
-
-
-
-
1.0
2.0
-
-
1.0
2.0
µA
µA
ON-state leakage current
supply current
VI = VIH or VIL; see Figure 10
VCC = 3.6 V
-
-
-
-
1.0
2.0
-
-
1.0
2.0
µA
µA
VCC = 6.0 V
VI = VCC or GND; IO = 0 A
VCC = 3.6 V
-
-
-
-
-
-
20
40
-
-
-
40
80
µA
µA
µA
VCC = 6.0 V
∆ICC
additional supply current
per input; VI = VCC − 0.6 V;
500
850
VCC = 2.7 V to 3.6 V
CI
input capacitance
switch capacitance
-
-
-
3.5
5
-
-
-
-
-
-
-
-
-
pF
pF
pF
Csw
independent pins nYn
common pins nZ
8
[1] Typical values are measured at Tamb = 25 °C.
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
7 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
9.1 Test circuits
V
V
CC
CC
S1 to S3
nY0
nY1
1
2
S1 to S3
nY0
nY1
1
2
V
or V
V
or V
IH
IL
IH IL
switch
switch
I
S
nZ
E
nZ
E
I
I
S
S
GND = V
GND = V
EE
EE
V
GND
CC
V
V
V
V
O
O
I
I
001aak345
001aak346
VI = VCC or VEE and VO = VEE or VCC
.
VI = VCC or VEE and VO = open circuit.
Fig 9. Test circuit for measuring OFF-state leakage
current
Fig 10. Test circuit for measuring ON-state leakage
current
9.2 ON resistance
Table 7.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
RON(peak) ON resistance (peak)
VI = 0 V to VCC − VEE
[2]
VCC = 1.2 V; ISW = 100 µA
VCC = 2.0 V; ISW = 1000 µA
VCC = 2.7 V; ISW = 1000 µA
VCC = 3.0 V to 3.6 V;
-
-
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
180
115
100
365
225
200
435
270
245
ISW = 1000 µA
VCC = 4.5 V; ISW = 1000 µA
VCC = 6.0 V; ISW = 1000 µA
-
-
75
70
150
140
-
-
180
165
Ω
Ω
∆RON
ON resistance mismatch VI = 0 V to VCC − VEE
between channels
[2]
VCC = 1.2 V; ISW = 100 µA
VCC = 2.0 V; ISW = 1000 µA
VCC = 2.7 V; ISW = 1000 µA
VCC = 3.0 V to 3.6 V;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
5
4
4
ISW = 1000 µA
VCC = 4.5 V; ISW = 1000 µA
VCC = 6.0 V; ISW = 1000 µA
-
-
3
2
-
-
-
-
-
-
Ω
Ω
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
8 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
Table 7.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
RON(rail) ON resistance (rail)
VI = GND
[2]
VCC = 1.2 V; ISW = 100 µA
VCC = 2.0 V; ISW = 1000 µA
VCC = 2.7 V; ISW = 1000 µA
VCC = 3.0 V to 3.6 V;
-
-
-
-
250
120
75
-
-
-
-
-
-
Ω
Ω
Ω
Ω
280
170
155
325
195
180
70
ISW = 1000 µA
VCC = 4.5 V; ISW = 1000 µA
VCC = 6.0 V; ISW = 1000 µA
VI = VCC − VEE
-
-
50
45
120
105
-
-
135
120
Ω
Ω
RON(rail) ON resistance (rail)
[2]
VCC = 1.2 V; ISW = 100 µA
VCC = 2.0 V; ISW = 1000 µA
VCC = 2.7 V; ISW = 1000 µA
VCC = 3.0 V to 3.6 V;
-
-
-
-
350
170
105
95
-
-
-
-
-
-
Ω
Ω
Ω
Ω
340
210
190
400
250
225
ISW = 1000 µA
VCC = 4.5 V; ISW = 1000 µA
VCC = 6.0 V; ISW = 1000 µA
-
-
70
65
140
125
-
-
165
150
Ω
Ω
[1] Typical values are measured at Tamb = 25 °C.
[2] When supply voltages (VCC − VEE) near 1.2 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
1.2 V, it is recommended to use these devices only for transmitting digital signals.
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
9 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
9.3 On resistance waveform and test circuit
V
V
V
SW
CC
S1 to S3
nY0
nY1
1
V
or V
IL
IH
switch
nZ
E
2
GND = V
EE
GND
I
V
SW
I
001aak347
RON = VSW / ISW
.
Fig 11. Test circuit for measuring RON
001aak348
200
V
= 2.0 V
CC
R
ON
(Ω)
150
V
= 3.0 V
CC
100
50
0
V
= 4.5 V
CC
0
1.2
2.4
3.6
4.8
V (V)
I
Vi = 0 V to VCC − VEE
Fig 12. Typical RON as a function of input voltage
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
10 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C
Min
Typ[1] Max
−40 °C to +125 °C
Unit
Min
Max
[2]
tpd
propagation delay nYn, nZ to nZ, nYn; see Figure 13
VCC = 1.2 V
-
-
-
-
-
-
25
9
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
17
13
10
9
20
15
12
10
8
VCC = 2.7 V
6
[3]
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V
5
4
VCC = 6.0 V
3
7
ten
enable time
E to nYn, nZ; see Figure 14
VCC = 1.2 V
-
-
-
-
-
-
-
100
34
25
16
19
17
13
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
65
48
-
77
56
-
VCC = 2.7 V
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V
38
32
25
45
38
29
VCC = 6.0 V
[2]
Sn to nYn, nZ; see Figure 14
VCC = 1.2 V
-
-
-
-
-
-
-
125
43
31
20
24
21
16
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
82
60
-
97
71
-
VCC = 2.7 V
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V
48
41
31
57
48
37
VCC = 6.0 V
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
11 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min
Typ[1] Max
−40 °C to +125 °C
Unit
Min
Max
[2]
tdis
disable time
E to nYn, nZ; see Figure 14
VCC = 1.2 V
-
-
-
-
-
-
-
95
34
26
17
20
18
15
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
61
46
-
73
54
-
VCC = 2.7 V
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V
37
32
25
44
38
30
VCC = 6.0 V
[2]
Sn to nYn, nZ; see Figure 14
VCC = 1.2 V
-
-
-
-
-
-
-
-
90
32
24
16
19
17
14
36
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
pF
VCC = 2.0 V
59
44
-
70
52
-
VCC = 2.7 V
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V
36
31
24
-
42
36
28
-
VCC = 6.0 V
[4]
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ((CL + CSW) × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
CSW = maximum switch capacitance in pF;
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
12 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
10.1 Waveforms
V
CC
nYn or nZ
input
V
M
V
EE
t
t
PLH
PHL
V
O
nZ or nYn
output
V
M
V
EE
001aak351
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 13. nYn, nZ to nZ, nYn propagation delays
V
CC
Sn, E input
V
M
V
V
V
SS
t
t
PLZ
PZL
V
O
90 %
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
10 %
EE
t
t
PHZ
PZH
V
O
90 %
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
10 %
switch ON
001aak352
EE
switch ON
switch OFF
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 14. Enable and disable times
Table 9. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VX
VY
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
VOL + 0.1VCC
VOL + 0.3 V
V
V
V
OH − 0.1VCC
2.7 V to 3.6 V
> 3.6 V
OH − 0.3 V
0.5VCC
VOL + 0.1VCC
OH − 0.1VCC
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
13 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
V
EE
001aak353
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 15. Test circuit for measuring switching times
Table 10. Test data
Supply voltage Input
Load
CL
VEXT
VCC
VI
tr, tf
RL
tPHL, tPLH
open
tPZH, tPHZ
VEE
tPZL, tPLZ
2VCC
< 2.7 V
VCC
2.7 V
VCC
≤ 6 ns
≤ 6 ns
≤ 6 ns
50 pF
1 kΩ
2.7 V to 3.6 V
> 3.6 V
15 pF, 50 pF 1 kΩ
50 pF 1 kΩ
open
VEE
2VCC
open
VEE
2VCC
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
14 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
10.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf ≤ 6.0 ns; Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
THD
total harmonic
distortion
fi = 1 kHz; CL = 50 pF; RL = 10 kΩ; see Figure 20
VCC = 3.0 V; VI = 2.75 V (p-p)
VCC = 6.0 V; VI = 5.5 V (p-p)
fi = 10 kHz; CL = 50 pF; RL = 10 kΩ; see Figure 20
VCC = 3.0 V; VI = 2.75 V (p-p)
VCC = 6.0 V; VI = 5.5 V (p-p)
CL = 50 pF; RL = 50 Ω; see Figure 16
VCC = 3.0 V
-
-
0.8
-
-
%
%
0.4
-
-
2.4
1.2
-
-
%
%
[1]
[2]
[2]
f(−3dB)
−3 dB frequency
response
-
-
180
200
-
-
MHz
MHz
VCC = 6.0 V
αiso
isolation (OFF-state)
crosstalk voltage
fi = 1 MHz; CL = 50 pF; RL = 600 Ω; see Figure 18
VCC = 3.0 V
-
-
−50
−50
-
-
dB
dB
VCC = 6.0 V
Vct
between digital inputs and switch;
fi = 1 MHz; CL = 50 pF; RL = 600 Ω; see Figure 21
VCC = 3.0 V
VCC = 6.0 V
-
-
0.11
0.12
-
-
V
V
Xtalk
crosstalk
between switches; fi = 1 MHz; CL = 50 pF;
RL = 600 Ω; see Figure 22
VCC = 3.0 V
VCC = 6.0 V
-
-
−60
−60
-
-
dB
dB
[1] Adjust fi voltage to obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 50 Ω).
[2] Adjust fi voltage to obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 600 Ω).
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
15 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
10.2.1 Test circuits
001aak361
5
(dB)
V
V
CC
CC
0
2R
L
S1 to S3
nY0
nY1
1
2
V
IH
or V
IL
switch
nZ
E
0.1 µF
GND = V
EE
2R
L
C
L
GND
dB
f
i
−5
2
3
4
5
6
10
10
10
10
10
10
f (kHz)
001aak355
VCC = 3.0 V; GND = 0 V; VEE = −3.0 V; RL = 50 Ω;
RSOURCE = 1 kΩ.
Fig 16. Test circuit for measuring frequency response
Fig 17. Typical frequency response
001aak360
0
(dB)
V
V
CC
CC
−50
2R
L
S1 to S3
nY0
nY1
1
2
V
or V
IL
IH
switch
nZ
E
0.1 µF
GND = V
EE
V
2R
L
C
L
dB
CC
f
i
−100
2
3
4
5
6
10
10
10
10
10
10
f (kHz)
001aak356
VCC = 3.0 V; GND = 0 V; VEE = −3.0 V; RL = 50 Ω;
RSOURCE = 1 kΩ.
Fig 18. Test circuit for measuring isolation (OFF-state) Fig 19. Typical isolation (OFF-state) as function of
frequency
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
16 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
V
V
CC
CC
2R
L
S1 to S3
nY0
nY1
1
2
V
IH
or V
IL
switch
nZ
E
10 µF
GND = V
EE
2R
L
C
L
GND
D
f
i
001aak354
Fig 20. Test circuit for measuring total harmonic distortion
V
V
V
CC
CC
CC
2R
2R
L
L
L
S1 to S3
nY0
nY1
1
switch
nZ
E
2
G
GND = V
EE
2R
2R
C
L
V
O
V
L
V
or V
IH
IL
001aak357
a. Test circuit
logic
input (Sn, E)
off
on
off
V
V
ct
O
001aaj908
b. Input and output pulse definitions
VI may be connected to Sn or E.
Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
17 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
V
V
V
CC
CC
CC
2R
L
2R
L
S1 to S3
nY0
nY1
V
IH
or V
IL
R
L
nZ
E
0.1 µF
GND = V
EE
2R
L
V
C
L
2R
L
GND
dB
O
V
I
001aak358
a. Switch closed condition
V
V
V
V
CC
CC
CC
CC
2R
L
2R
2R
L
L
L
S1 to S3
nY0
nY1
V
or V
IL
IH
nZ
E
GND = V
EE
GND
R
L
V
I
2R
2R
L
C
L
V
dB
O
001aak359
b. Switch open condition
Fig 22. Test circuit for measuring crosstalk between switches
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
18 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
11. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 23. Package outline SOT38-4 (DIP16)
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
19 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 24. Package outline SOT109-1 (SO16)
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
20 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 25. Package outline SOT338-1 (SSOP16)
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
21 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 26. Package outline SOT403-1 (TSSOP16)
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
22 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 27. Package outline SOT763-1 (DHVQFN16)
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
23 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
12. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
ESD
Description
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 13. Revision history
Document ID
74LV4053_4
Modifications:
Release date
20090810
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV4053_3
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74LV4053BQ (DHVQFN16 package)
• RON values changed in Section 2.
• Package version SOT38-1 changed to SOT38-4 in Section 3, and Figure 23.
74LV4053_3
74LV4053_2
19980623
Product specification
-
74LV4053_2
19970715
Product specification
-
-
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
24 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LV4053_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 August 2009
25 of 26
74LV4053
NXP Semiconductors
Triple single-pole double-throw analog switch
16. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
7
8
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
9
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 8
On resistance waveform and test circuit. . . . . 10
9.1
9.2
9.3
10
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Additional dynamic parameters . . . . . . . . . . . 15
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10.1
10.2
10.2.1
11
12
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14.1
14.2
14.3
14.4
15
16
Contact information. . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 August 2009
Document identifier: 74LV4053_4
相关型号：
74LV4053PWDH-T
IC TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16, PLASTIC, TSSOP-16, Multiplexer or Switch
NXP
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