74LV573PW,112 [NXP]
74LV573 - Octal D-type transparent latch; 3-state TSSOP2 20-Pin;型号: | 74LV573PW,112 |
厂家: | NXP |
描述: | 74LV573 - Octal D-type transparent latch; 3-state TSSOP2 20-Pin 驱动 光电二极管 逻辑集成电路 |
文件: | 总18页 (文件大小:113K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LV573
Octal D-type transparent latch; 3-state
Rev. 03 — 15 April 2009
Product data sheet
1. General description
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC573 and 74HCT573.
The 74LV573 consists of eight D-type transparent latches, featuring separate D-type
inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable
(LE) input and an output enable (OE) input are common to all internal latches.
When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches
are transparent, that is, a latch output will change each time its corresponding D-input
changes. When LE is LOW, the latches store the information that was present at the
D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the outputs. When OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the latches.
The 74LV573 is functionally identical to the 74LV373, but has a different pin arrangement.
2. Features
I Wide operating voltage: 1.0 V to 5.5 V
I Optimized for low voltage applications: 1.0 V to 3.6 V
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 °C
I Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
I Useful as input or output port for microprocessors
I Common 3-state output enable input
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LV573N
74LV573D
−40 °C to +125 °C
−40 °C to +125 °C
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
SOT163-1
plastic small outline package; 20 leads;
body width 7.5 mm
74LV573DB
74LV573PW
−40 °C to +125 °C
−40 °C to +125 °C
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
SOT360-1
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
4. Functional diagram
11
C1
1
EN1
1
2
19
1D
OE
2
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
4
5
18
17
16
3
4
5
6
7
8
9
6
7
8
9
15
14
13
12
LE
11
mna807
mna808
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
2 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
2
3
4
5
6
7
8
9
19
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1 18
17
16
15
14
13
12
Q2
Q3
LATCH
1 to 8
3-STATE
OUTPUTS Q4
Q5
Q6
Q7
LE
11
1
OE
mna809
Fig 3. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna810
Fig 4. Logic diagram
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
3 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
74LV573
74LV573
1
2
20
19
18
17
16
15
14
13
12
11
1
2
20
19
18
17
16
15
14
13
12
11
OE
D0
V
OE
D0
V
CC
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
3
3
D1
D1
4
4
D2
D2
5
5
D3
D3
6
6
D4
D4
7
7
D5
D5
8
8
D6
D6
9
9
D7
D7
10
10
GND
GND
001aaj966
001aaj967
Fig 5. Pin configuration DIP20, SO20
Fig 6. Pin configuration SSOP20, TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
output enable input (active LOW)
data input
D0 to D7
GND
2, 3, 4, 5, 6, 7, 8, 9
10
ground (0 V)
LE
11
latch enable input (active HIGH)
data output
Q0 to Q7
VCC
19, 18, 17, 16, 15, 14, 13, 12
20
supply voltage
6. Functional description
Table 3.
Functional table[1]
Operating modes
Input
Internal latch Output
Qn
OE
L
LE
H
H
L
Dn
L
H
l
Enable and read register
(transparent mode)
L
L
L
H
L
H
L
Latch and read register
L
L
L
h
l
H
L
H
Z
Z
Latch register and disable outputs
H
H
L
L
h
H
[1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
4 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
20
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
-
mA
mA
mA
mA
mA
°C
IOK
-
50
IO
-
35
ICC
supply current
-
70
IGND
Tstg
Ptot
ground current
−70
−65
-
storage temperature
total power dissipation
+150
[2]
Tamb = −40 °C to +125 °C
DIP20
-
-
750
500
mW
mW
SO20, SSOP20 and TSSOP20
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP20 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
Parameter
supply voltage[1]
Conditions
Min
Typ
Max
5.5
Unit
1.0
3.3
V
VI
input voltage
0
-
VCC
VCC
V
VO
output voltage
0
-
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
+25
+125
500
200
100
50
°C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
5 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input voltage
VCC = 1.2 V
0.9
-
-
-
-
-
-
-
-
-
0.9
-
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.4
-
-
1.4
-
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
2.0
2.0
0.7VCC
-
0.7VCC
-
VIL
LOW-level input voltage
HIGH-level output voltage
-
-
-
-
0.3
0.6
0.8
0.3VCC
-
-
-
-
0.3
0.6
0.8
0.3VCC
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
VOH
IO = −100 µA; VCC = 1.2 V
IO = −100 µA; VCC = 2.0 V
IO = −100 µA; VCC = 2.7 V
IO = −100 µA; VCC = 3.0 V
IO = −100 µA; VCC = 4.5 V
IO = −8 mA; VCC = 3.0 V
IO = −16 mA; VCC = 4.5 V
VI = VIH or VIL
-
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
1.8
2.5
2.8
4.3
2.4
3.6
1.8
2.5
2.8
4.3
2.2
3.5
VOL
LOW-level output voltage
IO = 100 µA; VCC = 1.2 V
IO = 100 µA; VCC = 2.0 V
IO = 100 µA; VCC = 2.7 V
IO = 100 µA; VCC = 3.0 V
IO = 100 µA; VCC = 4.5 V
IO = 8 mA; VCC = 3.0 V
IO = 16 mA; VCC = 4.5 V
VI = VCC or GND;
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
V
0.2
0.2
0.2
0.2
0.40
0.55
1.0
0.2
0.2
0.2
0.2
0.50
0.65
1.0
V
0
V
0
V
0
V
0.20
0.35
-
V
V
II
input leakage current
µA
VCC = 5.5 V
IOZ
OFF-state output current
VI = VIH or VIL;
-
-
5
-
10
µA
VO = VCC or GND;
V
CC = 5.5 V
VI = VCC or GND; IO = 0 A;
CC = 5.5 V
per input; VI = VCC − 0.6 V;
CC = 2.7 V to 3.6 V
ICC
∆ICC
CI
supply current
-
-
-
-
-
20
500
-
-
-
-
160
850
-
µA
µA
pF
V
additional supply current
input capacitance
V
3.5
[1] Typical values are measured at Tamb = 25 °C.
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
6 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11.
Symbol Parameter Conditions −40 °C to +85 °C
Min
Typ[1] Max
−40 °C to +125 °C
Unit
Min
Max
[2]
tpd
propagation delay Dn to Qn; see Figure 7
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
-
-
-
-
-
-
75
26
19
12
14
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
39
29
-
49
36
-
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
LE to Qn; see Figure 8
VCC = 1.2 V
23
19
29
24
[2]
-
-
-
-
-
-
80
27
20
13
15
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
43
31
-
53
34
-
VCC = 2.7 V
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
OE to Qn; see Figure 9
VCC = 1.2 V
25
21
31
26
[2]
ten
enable time
-
-
-
-
-
70
24
18
13
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
37
28
22
18
48
35
28
23
VCC = 2.7 V
[3]
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
OE to Qn; see Figure 9
VCC = 1.2 V
tdis
disable time
-
-
-
-
-
80
29
22
17
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
39
29
24
20
48
36
29
24
VCC = 2.7 V
[3]
[3]
[3]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
LE HIGH; see Figure 8
VCC = 2.0 V
tW
pulse width
set-up time
34
25
20
9
6
5
-
-
-
41
30
24
-
-
-
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
nD to nCP; see Figure 10
VCC = 1.2 V
tsu
-
25
9
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
17
13
10
20
15
12
VCC = 2.7 V
6
VCC = 3.0 V to 3.6 V
5
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
7 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min
Typ[1] Max
−40 °C to +125 °C
Unit
Min
Max
th
hold time
Dn to LE; see Figure 10
VCC = 1.2 V
-
8
8
8
-
5
2
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
pF
VCC = 2.0 V
8
8
8
-
VCC = 2.7 V
2
[3]
[4]
VCC = 3.0 V to 3.6 V
1
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
26
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
V
I
V
M
Dn input
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
mna811
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Input (Dn) to output (Qn) propagation delays
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
8 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
1/f
max
V
I
LE input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
M
Qn output
mna812
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays
V
I
OE input
V
M
t
GND
t
PLZ
PZL
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna813
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Enable and disable times
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
9 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
V
I
V
M
Dn input
GND
t
t
h
h
t
t
su
su
V
I
LE input
V
M
GND
mna814
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. Data set-up and hold times for the Dn input to the LE input
Table 8.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VX
VY
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
VOL + 0.1VCC
VOL + 0.3 V
V
V
V
OH − 0.1VCC
2.7 V to 3.6 V
≥ 4.5 V
OH − 0.3 V
0.5VCC
VOL + 0.1VCC
OH − 0.1VCC
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
10 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
r
f
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 11. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage Input
Load
CL
VEXT
VCC
VI
tr, tf
RL
tPHL, tPLH
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCC
< 2.7 V
VCC
2.7 V
VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
50 pF
1 kΩ
2.7 V to 3.6 V
≥ 4.5 V
15 pF, 50 pF 1 kΩ
50 pF 1 kΩ
open
GND
2VCC
open
GND
2VCC
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
11 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
12. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 12. Package outline SOT146-1 (DIP20)
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
12 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 13. Package outline SOT163-1 (SO20)
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
13 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 14. Package outline SOT339-1 (SSOP20)
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
14 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 15. Package outline SOT360-1 (TSSOP20)
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
15 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74LV573_3
Release date
20090415
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV573_2
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name when appropriate.
74LV573_2
74LV573_1
19980610
Product specification
-
74LV573_1
19970606
Product specification
-
-
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
16 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
17 of 18
74LV573
NXP Semiconductors
Octal D-type transparent latch; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 April 2009
Document identifier: 74LV573_3
相关型号:
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