74LV574A [TI]
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS; 八路边沿触发D型触发器型号: | 74LV574A |
厂家: | TEXAS INSTRUMENTS |
描述: | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS |
文件: | 总20页 (文件大小:846K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢃ ꢇꢈ ꢀꢁꢆ ꢃꢄꢅ ꢂꢆ ꢃꢇ
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SCLS412I − APRIL 1998 − REVISED APRIL 2005
D
D
D
D
D
2-V to 5.5-V V
Operation
D
D
D
I
Supports Partial-Power-Down Mode
CC
off
Operation
Max t of 10 ns at 5 V
pd
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Support Mixed-Mode Voltage Operation on
All Ports
− 1000-V Charged-Device Model (C101)
SN54LV574A . . . FK PACKAGE
SN54LV574A . . . J OR W PACKAGE
SN74LV574A . . . DB, DGV, DW, NS,
OR PW PACKAGE
SN74LV574A . . . RGY PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1
20
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1Q
1
2
3
4
5
6
7
8
9
10
20
19
3
2 1 20 19
3D
4D
5D
6D
7D
2Q
3Q
4Q
18
17
16
4
5
6
7
8
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
18 2Q
17
16
15
14
13
12
11
3Q
4Q
5Q
6Q
7Q
8Q
CLK
15 5Q
14
6Q
9 10 11 12 13
10
11
GND
description/ordering information
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74LV574ARGYR
SN74LV574ADW
SN74LV574ADWR
SN74LV574ANSR
SN74LV574ADBR
SN74LV574APW
SN74LV574APWR
SN74LV574APWT
SN74LV574ADGVR
SN74LV574AGQNR
SNJ54LV574AJ
QFN − RGY
SOIC − DW
Reel of 1000
Tube of 25
LV574A
LV574A
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
SOP − NS
74LV574A
LV574A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Reel of 1000
Tube of 20
TSSOP − PW
LV574A
TVSOP − DGV
VFBGA − GQN
CDIP − J
LV574A
LV574A
SNJ54LV574AJ
SNJ54LV574AW
SNJ54LV574AFK
−55°C to 125°C CFP − W
Tube of 85
SNJ54LV574AW
LCCC − FK
Tube of 55
SNJ54LV574AFK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢃꢇ ꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢂ ꢆꢃ ꢇ
ꢉꢊ ꢋꢇ ꢄ ꢌꢍ ꢎꢌꢏ ꢋꢐ ꢑꢎ ꢎꢌ ꢐꢌ ꢍ ꢍꢏꢋ ꢒ ꢓꢌ ꢔꢄ ꢑ ꢓꢏꢔ ꢄ ꢉ ꢓꢀ
ꢕꢑ ꢋ ꢖ ꢗ ꢏꢀꢋꢇꢋ ꢌ ꢉꢘꢋ ꢓ ꢘꢋꢀ
SCLS412I − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
The ’LV574A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V V
operation.
CC
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data
(D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
GQN PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
1
1D
2
3
4
A
B
C
D
E
A
B
C
D
E
OE
3Q
4D
7Q
8D
V
1Q
2Q
4Q
6Q
8Q
CC
3D
2D
5Q
5D
7D
6D
GND
CLK
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢃ ꢇꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢂꢆ ꢃꢇ
ꢉ ꢊꢋꢇꢄ ꢌꢍꢎ ꢌ ꢏꢋꢐ ꢑꢎ ꢎꢌ ꢐꢌꢍ ꢍꢏꢋ ꢒꢓ ꢌ ꢔ ꢄꢑ ꢓ ꢏꢔ ꢄꢉ ꢓꢀ
ꢕ ꢑꢋ ꢖ ꢗ ꢏꢀꢋꢇꢋ ꢌ ꢉ ꢘꢋ ꢓꢘ ꢋꢀ
SCLS412I − APRIL 1998 − REVISED APRIL 2005
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
19
1Q
2
1D
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, FK, J, NS, PW, RGY, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range applied in the high or low state, V (see Notes 1 and 2) . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢃꢇ ꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢂ ꢆꢃ ꢇ
ꢉꢊ ꢋꢇ ꢄ ꢌꢍ ꢎꢌꢏ ꢋꢐ ꢑꢎ ꢎꢌ ꢐꢌ ꢍ ꢍꢏꢋ ꢒ ꢓꢌ ꢔꢄ ꢑ ꢓꢏꢔ ꢄ ꢉ ꢓꢀ
ꢕꢑ ꢋ ꢖ ꢗ ꢏꢀꢋꢇꢋ ꢌ ꢉꢘꢋ ꢓ ꢘꢋꢀ
SCLS412I − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV574A
SN74LV574A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
V
V
V
V
V
V
V
= 2 V
1.5
1.5
CC
CC
CC
CC
CC
CC
CC
CC
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
V
V
V
× 0.3
× 0.3
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
V
V
Input voltage
0
0
0
5.5
0
0
0
5.5
I
High or low state
3-state
V
V
CC
5.5
CC
5.5
Output voltage
V
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−8
−16
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−8
mA
−16
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
8
8
mA
16
16
200
100
20
85
200
100
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV574A
SN74LV574A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −8 mA
= −16 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
V
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 8 mA
3 V
= 16 mA
4.5 V
I
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
µA
pF
I
I
V
= V or GND
O CC
or GND,
5
5
OZ
CC
off
V = V
CC
I
O
= 0
5.5 V
20
20
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
1.8
1.8
i
I
CC
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ꢜ
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢃ ꢇꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢂꢆ ꢃꢇ
ꢉ ꢊꢋꢇꢄ ꢌꢍꢎ ꢌ ꢏꢋꢐ ꢑꢎ ꢎꢌ ꢐꢌꢍ ꢍꢏꢋ ꢒꢓ ꢌ ꢔ ꢄꢑ ꢓ ꢏꢔ ꢄꢉ ꢓꢀ
ꢕ ꢑꢋ ꢖ ꢗ ꢏꢀꢋꢇꢋ ꢌ ꢉ ꢘꢋ ꢓꢘ ꢋꢀ
SCLS412I − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV574A SN74LV574A
A
PARAMETER
UNIT
MIN
7
MAX
MIN
7
MAX
MIN
7
MAX
t
w
t
su
t
h
Pulse duration
Setup time
Hold time
CLK high or low
ns
ns
ns
High or low before CLK↑
Data after CLK↑
5.5
2
5.5
2
5.5
2
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV574A SN74LV574A
A
PARAMETER
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration
Setup time
Hold time
CLK high or low
ns
ns
ns
High or low before CLK↑
Data after CLK↑
3.5
1.5
3.5
1.5
3.5
1.5
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV574A SN74LV574A
A
PARAMETER
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration
Setup time
Hold time
CLK high or low
ns
ns
ns
High or low before CLK↑
Data after CLK↑
3.5
1.5
3.5
1.5
3.5
1.5
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
100*
85
SN54LV574A SN74LV574A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
60*
50
MAX
MIN
50*
40
1*
1*
1*
1
MAX
MIN
50
40
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
t
t
t
CLK
OE
9.6* 16.6*
9.2* 16.1*
6.5* 12.8*
20*
19*
15*
23
20
19
15
23
22
20
2
Q
Q
Q
Q
Q
Q
pd
1
ns
ns
C
C
= 15 pF
= 50 pF
en
L
L
1
OE
dis
pd
CLK
OE
11.6
10.9
8.4
19.6
19
1
1
22
1
en
17.5
2
1
20
1
OE
dis
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢓ
ꢐ
ꢉ
ꢍ
ꢘ
ꢊ
ꢋ
ꢓ
ꢐ
ꢌ
ꢅ
ꢑ
ꢌ
ꢕ
ꢛ
ꢣ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢝꢢ ꢜ ꢛ ꢮꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢯ ꢢ ꢩꢞ ꢧꢡꢢ ꢣꢙꢪ ꢊ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢟ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢯ
ꢢ
ꢞ
ꢦ
ꢜ
ꢧ
ꢢ
ꢟ
ꢛ
ꢥ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢦ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢮ
ꢣ
ꢮ
ꢞ
ꢤ
ꢩ
ꢜ
ꢪ
ꢋ
ꢢ
ꢫ
ꢤ
ꢜ
ꢑ
ꢣ
ꢜ
ꢙ
ꢦ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞꢝ ꢠꢟꢙ ꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢯ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢃꢇ ꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢂ ꢆꢃ ꢇ
ꢉꢊ ꢋꢇ ꢄ ꢌꢍ ꢎꢌꢏ ꢋꢐ ꢑꢎ ꢎꢌ ꢐꢌ ꢍ ꢍꢏꢋ ꢒ ꢓꢌ ꢔꢄ ꢑ ꢓꢏꢔ ꢄ ꢉ ꢓꢀ
ꢕꢑ ꢋ ꢖ ꢗ ꢏꢀꢋꢇꢋ ꢌ ꢉꢘꢋ ꢓ ꢘꢋꢀ
SCLS412I − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV574A SN74LV574A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
80*
50
MAX
MIN
65*
45
MAX
MIN
65
45
1
MAX
145*
120
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
t
t
t
CLK
OE
6.8* 13.2*
6.4* 12.8*
1* 15.5*
15.5
15
Q
Q
Q
Q
Q
Q
pd
1*
1*
1
15*
15*
19
1
ns
ns
C
C
= 15 pF
= 50 pF
en
L
L
4.8*
8.1
7.7
6.1
13*
16.7
16.3
15
1
15
OE
dis
pd
CLK
OE
1
19
1
18.5
17
1
18.5
17
en
1
1
OE
dis
sk(o)
1.5
1.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
205*
175
4.8*
4.6*
3.5*
5.7
SN54LV574A SN74LV574A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
130*
85
MAX
MIN
110*
75
MAX
MIN
110
75
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
t
t
t
CLK
OE
8.6*
9*
1*
10*
10
10.5
10.5
12
Q
Q
Q
Q
Q
Q
pd
1* 10.5*
1* 10.5*
1
ns
ns
C
C
= 15 pF
= 50 pF
en
L
L
9*
1
OE
dis
pd
CLK
OE
10.6
11
1
1
1
12
12.5
11.5
1
5.5
1
12.5
11.5
1
en
4.1
10.1
1
1
OE
dis
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 6)
CC
L
A
SN74LV574A
PARAMETER
UNIT
MIN
TYP
0.7
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.6
2.8
−0.8
OL
OH
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
20.4
23.8
UNIT
CC
3.3 V
C
Power dissipation capacitance
Outputs enabled
C
pF
pd
5 V
ꢓ
ꢐ
ꢉ
ꢍ
ꢘ
ꢊ
ꢋ
ꢓ
ꢐ
ꢌ
ꢅ
ꢑ
ꢌ
ꢕ
ꢛ
ꢣ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢮ ꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢯ ꢢ ꢩ ꢞꢧ ꢡꢢ ꢣ ꢙꢪ ꢊ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢯ
ꢢ
ꢞ
ꢦ
ꢜ
ꢧ
ꢢ
ꢟ
ꢛ
ꢥ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢦ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢮ
ꢣ
ꢮ
ꢞ
ꢤ
ꢩ
ꢜ
ꢪ
ꢋ
ꢢ
ꢫ
ꢤ
ꢜ
ꢑ
ꢣ
ꢜ
ꢙ
ꢦ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚ ꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞ ꢝꢠꢟ ꢙꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢯ
ꢢꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢃ ꢇꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢂꢆ ꢃꢇ
ꢉ ꢊꢋꢇꢄ ꢌꢍꢎ ꢌ ꢏꢋꢐ ꢑꢎ ꢎꢌ ꢐꢌꢍ ꢍꢏꢋ ꢒꢓ ꢌ ꢔ ꢄꢑ ꢓ ꢏꢔ ꢄꢉ ꢓꢀ
ꢕ ꢑꢋ ꢖ ꢗ ꢏꢀꢋꢇꢋ ꢌ ꢉ ꢘꢋ ꢓꢘ ꢋꢀ
SCLS412I − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
t
CC
CC
0 V
0 V
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN74LV574ADBR
SN74LV574ADBRE4
SN74LV574ADGVR
SN74LV574ADGVRE4
SN74LV574ADW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
TVSOP
TVSOP
SOIC
DB
DGV
DGV
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV574ADWE4
SN74LV574ADWR
SN74LV574ADWRE4
SN74LV574AGQNR
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQN
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LV574ANSR
SN74LV574ANSRE4
SN74LV574APW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
PW
PW
PW
PW
RGY
RGY
ZQN
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV574APWE4
SN74LV574APWR
SN74LV574APWRE4
SN74LV574APWT
SN74LV574APWTE4
SN74LV574ARGYR
SN74LV574ARGYRG4
SN74LV574AZQNR
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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