74LVC06AD,118 [NXP]
74LVC06A - Hex inverter with open-drain outputs SOIC 14-Pin;
| 型号： | 74LVC06AD,118 |
| 厂家： | 
NXP |
| 描述： | 74LVC06A - Hex inverter with open-drain outputs SOIC 14-Pin 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC06A
Hex inverter with open-drain
outputs
Product specification
2003 Nov 27
Supersedes data of 2003 Aug 28
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
FEATURES
DESCRIPTION
• 5 V tolerant inputs and outputs (open drain) for
interfacing with 5 V logic
The 74LVC06A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
• Wide supply voltage range from 1.65 to 5.5 V
• CMOS low power consumption
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 to 5 V environment.
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
The 74LVC06A provides six inverting buffers.
• Complies with JEDEC standard no. 8-1A
The outputs of the 74LVC06A are open drain and can be
connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND
functions.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PLZ/tPZL
CI
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
propagation delay nA to nY
input capacitance
CL = 50 pF; VCC = 3.3 V
2.3
5.0
8.0
ns
pF
pF
CPD
power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nA
L
nY
Z
H
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
2003 Nov 27
2
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC06AD
74LVC06APW
74LVC06ABQ
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
14
14
14
SO14
plastic
plastic
plastic
SOT108-1
SOT402-1
SOT762-1
TSSOP14
DHVQFN14
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
1A
1Y
2A
2Y
3A
3Y
GND
4Y
4A
5Y
5A
6Y
6A
VCC
data input
data output
data input
3
4
data output
data input
5
6
data output
ground (0 V)
data output
data input
7
8
9
10
11
12
13
14
data output
data input
data output
data input
supply voltage
V
1A
1
handbook, halfpage
CC
handbook, halfpage
14
1A
1Y
2A
2Y
3A
3Y
1
2
3
4
5
6
7
14 V
CC
1Y
2A
2
3
13 6A
12 6Y
13 6A
12 6Y
11 5A
10 5Y
06
(1)
2Y
3A
3Y
4
5
6
GND
11 5A
10 5Y
9
8
4A
4Y
9
4A
GND
7
8
MNA524
GND 4Y
Top view
MBL760
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration (SO14 and TSSOP14).
Fig.2 Pin configuration (DHVQFN14).
2003 Nov 27
3
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
handbook, halfpage
handbook, halfpage
1
1
1
1
1
1
1
2
1
3
5
9
1A
2A
3A
4A
1Y
2Y
3Y
4Y
2
4
6
8
1A
2A
3A
4A
5A
6A
1Y
3
4
2Y
5
6
3Y
9
8
4Y
11 5A
13 6A
5Y 10
6Y 12
11
13
10
5Y
12
6Y
MNA526
MNA525
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
Y
handbook, halfpage
A
GND
MNA527
Fig.5 Logic diagram (one gate).
2003 Nov 27
4
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
5.5
UNIT
VCC
VI
V
V
V
V
input voltage
0
5.5
5.5
5.5
+125
20
VO
output voltage
active mode
0
high-impedance mode
0
Tamb
tr, tf
operating ambient temperature
input rise and fall ratios
−40
0
°C
VCC = 1.65 to 2.7 V
ns/V
ns/V
V
CC = 2.7 to 5.5 V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0
note 1
VO < 0
−
−50
mA
V
VI
−0.5
−
+6.5
−50
IOK
VO
output clamping diode current
output voltage
mA
V
active mode; note 1
−0.5
+6.5
+6.5
50
high-impedance mode; note 1 −0.5
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
VO = 0 to VCC
−
mA
mA
°C
mW
I
CC, IGND
−
±100
+150
500
Tstg
Ptot
−65
−
Tamb = −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
2003 Nov 27
5
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input
1.65 to 1.95 VCC
−
−
−
−
−
V
voltage
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
−
−
−
−
−
−
−
V
V
V
V
V
V
V
2.0
0.7 × VCC
VIL
LOW-level input voltage
−
−
−
−
GND
0.7
0.8
0.30 × VCC
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
−
−
−
−
−
−
−
−
−
0.20
0.45
0.3
V
−
V
IO = 8 mA
2.3
−
V
IO = 12 mA
IO = 24 mA
IO = 32 mA
VI = 5.5 V or GND
2.7
−
0.4
V
3.0
−
0.55
0.55
±5
V
4.5
−
V
ILI
input leakage current
1.65 to 5.5
1.65 to 5.5
±0.1
0.1
µA
µA
IOZ
output leakage current VI = VIH;
VO = 5.5 V or GND
±10
Ioff
power-off leakage
current
VI or VO = 5.5 V
0
−
−
−
±0.1
0.1
5
±10
10
µA
µA
µA
ICC
∆ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
additional quiescent
VI = VCC − 0.6 V;
2.3 to 5.5
500
supply current per input IO = 0
pin
Tamb = −40 to +125 °C
VIH HIGH-level input
1.65 to 1.95 0.65 x VCC
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
voltage
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
−
2.0
−
0.7 × VCC
−
VIL
LOW-level input voltage
−
−
−
−
0.35 × VCC
0.7
0.8
0.30 × VCC
2003 Nov 27
6
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
−
−
−
−
−
−
−
−
−
0.20
V
−
−
−
−
−
−
−
0.45
0.3
V
IO = 8 mA
2.3
V
IO = 12 mA
IO = 24 mA
IO = 32 mA
VI = 5.5 V or GND
2.7
0.4
V
3.0
0.55
0.55
±5
V
4.5
V
ILI
input leakage current
1.65 to 5.5
1.65 to 5.5
µA
µA
IOZ
output leakage current VI = VIH;
VO = 5.5 V or GND
±10
Ioff
power-off leakage
current
VI or VO = 5.5 V
0
−
−
−
−
−
−
±10
10
µA
µA
µA
ICC
∆ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
additional quiescent
VI = VCC − 0.6 V;
2.3 to 5.5
500
supply current per input IO = 0
pin
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2 ns for VCC ≤ 2.7 V and tr = tf ≤ 2.5 ns for VCC ≥ 2.7 V.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C; note 1
tPLZ/tPZL propagation delay nA to nY see Figs 6 and 7
1.65 to 1.95
2.3 to 2.7
2.7
−
2.9
−
ns
0.5
0.5
0.5
0.5
1.8
3.1
3.9
3.7
3.4
ns
ns
ns
ns
2.5
2.3(2)
3.0 to 3.6
4.5 to 5.5
1.7
Tamb = −40 to +125 °C
tPLZ/tPZL
propagation delay nA to nY see Figs 6 and 7
1.65 to 1.95
2.3 to 2.7
2.7
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
0.5
0.5
0.5
0.5
4.0
5.0
5.0
4.5
3.0 to 3.6
4.5 to 5.5
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Typical value is measured at VCC = 3.3 V.
2003 Nov 27
7
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
AC WAVEFORMS
V
I
V
nA input
M
GND
t
t
PZL
PLZ
V
CC
nY output
V
M
V
V
X
OL
MNA529
VCC
VM
VX
<2.7 V
0.5 × VCC
1.5 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
≥2.7 to 3.6 V
≥4.5 to 5.5 V
0.5 × VCC
Fig.6 The input nA to output nY propagation delays.
2003 Nov 27
8
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
V
ext
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
R
C
R
L
L
T
MNA530
VCC
Vext
VI
CL
30 pF
RL
1 kΩ
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
2 × VCC
2 × VCC
6 V
VCC
VCC
30 pF
50 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
VCC
3.0 to 3.6 V
4.5 to 5.5 V
6 V
2 × VCC
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
2003 Nov 27
9
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
2003 Nov 27
10
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
2003 Nov 27
11
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
2003 Nov 27
12
Philips Semiconductors
Product specification
Hex inverter with open-drain outputs
74LVC06A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Nov 27
13
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/03/pp14
Date of release: 2003 Nov 27
Document order number: 9397 750 12264
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