74LVC08APW-Q100,11 [NXP]

74LVC08A-Q100 - Quad 2-input AND gate TSSOP 14-Pin;


型号：	74LVC08APW-Q100,11
厂家：	NXP
描述：	74LVC08A-Q100 - Quad 2-input AND gate TSSOP 14-Pin 光电二极管逻辑集成电路
文件：	总12页 (文件大小：111K)
中文：	中文翻译
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74LV08-Q100

Quad 2-input AND gate

Rev. 1 — 31 July 2012

Product data sheet

1. General description

The 74LV08-Q100 is a low-voltage Si-gate CMOS device that is pin and function

compatible with 74HC08-Q100 and 74HCT08-Q100.

The 74LV08-Q100 provides a quad 2-input AND function.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Wide operating voltage: 1.0 V to 5.5 V

 Optimized for low voltage applications: 1.0 V to 3.6 V

 Accepts TTL input levels between V_CC= 2.7 V and V_CC= 3.6 V

 Typical output ground bounce < 0.8 V at V_CC= 3.3 V and T_amb= 25 C

 Typical HIGH-level output voltage (V_OH) undershoot: > 2 V at V_CC= 3.3 V and

T_amb= 25 C

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

40 C to +125 C SO14

Description

Version

74LV08D-Q100

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LV08PW-Q100 40 C to +125 C

TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

4. Functional diagram

mna221

4Y 11

mna222

mna223

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram (one gate)

5. Pinning information

5.1 Pinning

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢄ

ꢀ

ꢇ

ꢈ

ꢅ

ꢌ

ꢍ

ꢎ

ꢀꢅ

ꢀꢈ

ꢀꢇ

ꢀꢀ

ꢀꢐ

ꢑ

ꢀꢁ

ꢀꢄ

ꢂ

ꢃꢃ

ꢅꢄ

ꢅꢁ

ꢅꢆ

ꢈꢄ

ꢈꢁ

ꢈꢆ

ꢀ

ꢇ

ꢈ

ꢅ

ꢌ

ꢍ

ꢎ

ꢀꢅ

ꢀꢈ

ꢀꢇ

ꢀꢀ

ꢀꢐ

ꢑ

ꢀꢁ

ꢀꢄ

ꢂ

ꢃꢃ

ꢀꢆ

ꢅꢄ

ꢅꢁ

ꢅꢆ

ꢈꢄ

ꢈꢁ

ꢈꢆ

ꢀꢆ

ꢇꢁ

ꢇꢄ

ꢇꢆ

ꢏ

ꢉꢊꢋ

ꢏ

ꢉꢊꢋ

ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢆ

ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢇ

Fig 4. Pin configuration SO14

Fig 5. Pin configuration TSSOP14

74LV08_Q100

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Product data sheet

Rev. 1 — 31 July 2012

2 of 12

74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

5.2 Pin description

Table 2.

Pin description

Symbol

Description

data input

1A, 2A, 3A, 4A

1B, 2B, 3B, 4B

1Y, 2Y, 3Y, 4Y

GND

1, 4, 9, 12

2, 5, 10, 13

3, 6, 8, 11

data input

data output

ground (0 V)

supply voltage

V_CC

6. Functional description

Table 3.

Function selection^[1]

Input

Output

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7.0

20

50

25

Unit

supply voltage

0.5

[1]

input clamping current

output clamping current

output current

V_I< 0.5 V or V_I> V_CC+ 0.5 V

V_O< 0.5 V or V_O> V_CC+ 0.5 V

V_O= 0.5 V to (V_CC+ 0.5 V)

C

I_OK

I_O

I_CC

supply current

I_GND

T_stg

P_tot

ground current

50

65

storage temperature

total power dissipation

+150

500

[2]

T_amb= 40 C to +125 C

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO14 packages: above 70 C the value of P_totderates linearly with 8 mW/K.

For TSSOP14 packages: above 60 C the value of P_totderates linearly with 5.5 mW/K.

74LV08_Q100

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Product data sheet

Rev. 1 — 31 July 2012

3 of 12

74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

Parameter

supply voltage^[1]

Conditions

Min

Typ

Max

5.5

Unit

1.0

3.3

V_I

input voltage

V_CC

+125

500

200

100

V_O

output voltage

T_amb

t/V

ambient temperature

input transition rise and fall rate

40

+25

C

V_CC= 1.0 V to 2.0 V

V_CC= 2.0 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 3.6 V to 5.5 V

ns/V

[1] The static characteristics are guaranteed from V_CC= 1.2 V to V_CC= 5.5 V, but LV devices are guaranteed to function down to

V_CC= 1.0 V (with input levels GND or V_CC).

9. Static characteristics

Table 6.

Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

V_IH

HIGH-level input voltage

V_CC= 1.2 V

0.9

V_CC= 2.0 V

1.4

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_CC= 1.2 V

2.0

0.7V_CC

V_IL

LOW-level input voltage

HIGH-level output voltage

0.3

0.6

0.8

0.3V_CC

0.3

0.6

0.8

0.3V_CC

V_CC= 2.0 V

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_I= V_IHor V_IL

V_OH

I_O= 100 A; V_CC= 1.2 V

I_O= 100 A; V_CC= 2.0 V

I_O= 100 A; V_CC= 2.7 V

I_O= 100 A; V_CC= 3.0 V

I_O= 100 A; V_CC= 4.5 V

I_O= 6 mA; V_CC= 3.0 V

I_O= 12 mA; V_CC= 4.5 V

1.2

2.0

2.7

3.0

4.5

2.82

4.2

1.8

2.5

2.8

4.3

2.4

3.6

1.8

2.5

2.8

4.3

2.2

3.5

74LV08_Q100

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Product data sheet

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74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

Table 6.

Static characteristics …continued

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

V_OL

LOW-level output voltage

V_I= V_IHor V_IL

I_O= 100 A; V_CC= 1.2 V

I_O= 100 A; V_CC= 2.0 V

I_O= 100 A; V_CC= 2.7 V

I_O= 100 A; V_CC= 3.0 V

I_O= 100 A; V_CC= 4.5 V

I_O= 6 mA; V_CC= 3.0 V

I_O= 12 mA; V_CC= 4.5 V

V_I= V_CCor GND; V_CC= 5.5 V

0.2

0.50

0.65

1.0

0.2

0.25

0.35

0.2

0.40

0.55

1.0

I_I

input leakage current

supply current

A

I_CC

V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

20.0

I_CC

additional supply current

input capacitance

per input; V_I= V_CC 0.6 V;

V_CC= 2.7 V to 3.6 V

500

850

A

C_I

3.5

[1] Typical values are measured at T_amb= 25 C.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

GND = 0 V; For test circuit see Figure 7.

Symbol Parameter Conditions

40 C to +85 C

Min

Typ^[1]Max

40 C to +125 C

Unit

Min

Max

[2]

t_pd

propagation delay nA, nB to nY; see Figure 6

V_CC= 1.2 V

V_CC= 2.0 V

V_CC= 2.7 V

[3]

V_CC= 3.0 V to 3.6 V; C_L= 15 pF

V_CC= 3.0 V to 3.6 V

9.0

V_CC= 4.5 V to 5.5 V

[4]

C_PD

power dissipation C_L= 50 pF; f_i= 1 MHz;

capacitance

V_I= GND to V_CC

[1] All typical values are measured at T_amb= 25 C.

[2] _pdis the same as t_PLHand t_PHL

[3] Typical values are measured at nominal supply voltage (V_CC= 3.3 V).

[4] C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz, f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs.

74LV08_Q100

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Product data sheet

Rev. 1 — 31 July 2012

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74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

11. Waveforms

nA, nB input

GND

PLH

PHL

nY output

mna224

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 6. The input (nA, nB) to output (nY) propagation delays

Table 8.

Measurement points

Supply voltage

V_CC

Input

V_M

Output

V_M

< 2.7 V

0.5V_CC

1.5 V

0.5V_CC

1.5 V

0.5V_CC

2.7 V to 3.6 V

 4.5 V

PULSE

GENERATOR

DUT

50 pF

1 kΩ

001aaa663

Test data is given in Table 9.

Definitions test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

Fig 7. Load circuit for switching times

Table 9.

Test data

Supply voltage

V_CC

Input

V_I

t_r, t_f

< 2.7 V

V_CC

2.7 V

V_CC

 2.5 ns

2.7 V to 3.6 V

 4.5 V

74LV08_Q100

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Product data sheet

Rev. 1 — 31 July 2012

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74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

12. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

(A )

pin 1 index

detail X

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

UNIT

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

1.75

1.27

0.05

1.05

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Fig 8. Package outline SOT108-1 (SO14)

74LV08_Q100

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Product data sheet

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74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

1.1

0.65

0.25

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig 9. Package outline SOT402-1 (TSSOP14)

74LV08_Q100

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Product data sheet

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74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

13. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

Machine Model

HBM

TTL

Transistor-Transistor Logic

MIL

Military

14. Revision history

Table 11. Revision history

Document ID

Release date

20120731

Data sheet status

Change notice

Supersedes

74LV08_Q100 v.1

Product data sheet

74LV08_Q100

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Product data sheet

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74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

15.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

74LV08_Q100

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Product data sheet

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10 of 12

74LV08-Q100

NXP Semiconductors

Quad 2-input AND gate

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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NXP Semiconductors

Quad 2-input AND gate

17. Contents

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional description . . . . . . . . . . . . . . . . . . . 3

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9

Legal information. . . . . . . . . . . . . . . . . . . . . . . 10

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

15.1

15.2

15.3

15.4

Contact information. . . . . . . . . . . . . . . . . . . . . 11

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 31 July 2012

Document identifier: 74LV08_Q100

74LVC08APW-Q100,11 [NXP]

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