74LVC132A [NXP]
Quad 2-input NAND Schmitt trigger; 四2输入与非施密特触发器
| 型号： | 74LVC132A |
| 厂家： | 
NXP |
| 描述： | Quad 2-input NAND Schmitt trigger |
| 文件： | 总15页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC132A
Quad 2-input NAND Schmitt trigger
Rev. 01 — 15 December 2006
Product data sheet
1. General description
The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT− is defined as the input
hysteresis voltage VH.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V environment.
2. Features
■ Wide supply voltage range from 2.3 V to 3.6 V
■ 5 V tolerant inputs for interfacing with 5 V logic
■ CMOS low power consumption
■ Direct interface with TTL levels
■ Unlimited rise and fall times
■ Inputs accept voltages up to 5.5 V
■ Complies with JEDEC standard JESD8-B/JESD36
■ ESD protection:
◆ HBM JESD22-A114-D exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101-C exceeds 1000 V
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
■ Wave and pulse shaper
■ Astable multivibrator
■ Monostable multivibrator.
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC132AD
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74LVC132APW −40 °C to +125 °C
74LVC132ABQ −40 °C to +125 °C
TSSOP14
plastic thin shrink small outline package; 14 leads; body SOT402-1
width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
5. Functional diagram
1
3
&
&
&
1
2
1A
1B
2
1Y
2Y
3Y
3
6
8
4
5
4
5
2A
2B
6
9
9
3A
8
10 3B
10
A
B
12 4A
13 4B
12
13
4Y 11
Y
11
&
001aac532
mna212
mna246
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
2 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
74LVC132A
terminal 1
index area
74LVC132A
2
3
4
5
6
13
12
11
10
9
1B
4B
4A
4Y
3B
3A
1
2
3
4
5
6
7
14
13
12
11
10
9
1Y
2A
2B
2Y
1A
1B
V
CC
4B
4A
4Y
3B
3A
3Y
1Y
GND(1)
2A
2B
2Y
001aaf591
GND
8
Transparent top view
001aaf590
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
6.2 Pin description
Table 2.
Symbol
1A
Pin description
Pin
1
Description
data input
1B
2
data input
1Y
3
data output
data input
2A
4
2B
5
data input
2Y
6
data output
ground (0 V)
data output
data input
GND
3Y
7
8
3A
9
3B
10
11
12
13
14
data input
4Y
data output
data input
4A
4B
data input
VCC
supply voltage
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
3 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
7. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nB
L
nY
H
L
H
L
H
H
H
H
H
L
[1] H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−50
-
Max
+6.5
+6.5
VCC + 0.5
-
Unit
V
supply voltage
[1]
[1]
input voltage
V
VO
output voltage
V
IIK
input clamping current
output clamping current
output current
VI < 0 V
mA
mA
mA
mA
mA
°C
IOK
VO > VCC or VO < 0 V
VO = 0 V to VCC
±50
±50
100
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−100
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: Ptot derates linearly with 8 mW/K above 70 °C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Conditions
Symbol Parameter
Min
1.2
0
Typ
Max
3.6
Unit
V
VCC
VI
supply voltage
input voltage
-
-
-
-
5.5
V
VO
output voltage
ambient temperature
0
VCC
+125
V
Tamb
−40
°C
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
4 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
Tamb = −40 °C to +85 °C
VOH
HIGH-level output voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 3.6 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VI = VIH or VIL
V
V
V
V
V
V
CC − 0.2
-
-
-
-
-
-
-
V
V
V
V
V
V
CC − 0.45 -
CC − 0.5
CC − 0.5
CC − 0.6
CC − 0.8
-
-
-
-
VOL
LOW-level output voltage
IO = 100 µA; VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
0.2
0.45
0.6
0.4
0.55
±5
V
-
V
-
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
VCC = 3.6 V; VI = 5.5 V or GND
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
-
V
-
V
II
input leakage current
supply current
±0.1
0.1
5
µA
µA
µA
ICC
∆ICC
10
additional supply current
per input pin; VCC = 2.7 V to 3.6 V;
500
VI = VCC − 0.6 V; IO = 0 A
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND to VCC
-
4.0
-
pF
Tamb = −40 °C to +125 °C
VOH HIGH-level output voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 3.6 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VI = VIH or VIL
V
V
V
V
V
V
CC − 0.3
-
-
-
-
-
-
-
-
V
V
V
V
V
V
CC − 0.6
CC − 0.65 -
CC − 0.65 -
CC − 0.75 -
CC − 1
-
VOL
LOW-level output voltage
IO = 100 µA; VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
±20
40
V
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
VCC = 3.6 V; VI = 5.5 V or GND
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
V
V
II
input leakage current
supply current
µA
µA
mA
ICC
∆ICC
additional supply current
per input pin; VCC = 2.7 V to 3.6 V;
5
VI = VCC − 0.6 V; IO = 0 A
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
5 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay
nA, nB to nY; see Figure 6
VCC = 1.2 V
-
18.0
7.2
4.0
3.8
3.4
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.5
-
12.8
7.6
7.6
6.4
1.0
2.0
1.5
1.5
1.5
-
16.0
9.6
9.6
8.0
1.5
VCC = 3.0 V to 3.6 V
[3]
[4]
tsk(o)
CPD
output skew time
power dissipation
capacitance
per buffer; VI = GND to VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
10.5
10.8
11.4
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 3.0 V to 3.6 V
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
V
t
nA, nB input
M
t
PHL
PLH
nY output
V
M
mna213
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
6 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 8. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
Table 8.
Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
tPHZ, tPZH
GND
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
≤ 2 ns
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
open
GND
open
GND
open
GND
3.0 V to 3.6 V
open
GND
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
7 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
13. Transfer characteristics
Table 9.
Transfer characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
VT+
VT−
VH
positive-going
threshold voltage
see Figure 8 and Figure 9
VCC = 1.2 V
0.2
0.4
0.6
0.8
0.9
1.1
1.2
1.2
1.0
1.3
1.5
1.7
1.7
2
0.2
0.4
0.6
0.8
0.9
1.1
1.2
1.2
1.0
1.3
1.5
1.7
1.7
2
V
V
V
V
V
V
V
V
VCC = 1.65 V
VCC = 1.95 V
VCC = 2.3 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
2
2
VCC = 3.6 V
2
2
negative-going
threshold voltage
see Figure 8 and Figure 9
VCC = 1.2 V
0.12
0.15
0.25
0.4
0.75
0.85
0.95
1.1
0.12
0.15
0.25
0.4
0.75
0.85
0.95
1.1
V
V
V
V
V
V
V
V
VCC = 1.65 V
VCC = 1.95 V
VCC = 2.3 V
VCC = 2.5 V
0.4
1.2
0.4
1.2
VCC = 2.7 V
0.8
1.4
0.8
1.4
VCC = 3.0 V
0.8
1.5
0.8
1.5
VCC = 3.6 V
0.8
1.5
0.8
1.5
hysteresis voltage (VT+ − VT−); see Figure 8,
Figure 9 and Figure 10
VCC = 1.2 V
VCC = 1.65 V
VCC = 1.95 V
VCC = 2.3 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0.1
0.2
0.2
0.3
0.3
0.3
0.3
0.3
1.0
1.15
1.25
1.3
0.1
0.2
0.2
0.3
0.3
0.3
0.3
0.3
1.0
1.15
1.25
1.3
V
V
V
V
V
V
V
V
1.3
1.3
1.1
1.1
1.2
1.2
1.2
1.2
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
8 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
14. Waveforms transfer characteristics
V
O
V
T+
V
I
V
H
V
T−
V
I
V
V
H
O
V
V
T+
T−
mna207
mna208
Fig 8. Transfer characteristic
Fig 9. Definition of VT+, VT− and VH
mna582
5
I
CC
(mA)
4
3
2
1
0
0
0.6
1.2
1.8
2.4
3
V (V)
I
Fig 10. Typical transfer characteristic; VCC = 3.3 V
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
9 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
15. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 11. Package outline SOT108-1 (SO14)
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
10 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 12. Package outline SOT402-1 (TSSOP14)
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
11 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 13. Package outline SOT762-1 (DHVQFN14)
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
12 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
16. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
17. Revision history
Table 11. Revision history
Document ID
Release date
20061215
Data sheet status
Change notice
Supersedes
74LVC132A_1
Product data sheet
-
-
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
13 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
18.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
19. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC132A_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 15 December 2006
14 of 15
74LVC132A
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
20. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Transfer characteristics. . . . . . . . . . . . . . . . . . . 8
Waveforms transfer characteristics. . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
12
13
14
15
16
17
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 December 2006
Document identifier: 74LVC132A_1
相关型号：
74LVC132ABQ-Q100
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74LVC132AD-Q100
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